Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives

• US 9,933,485 B2
• Filed: 02/23/2016
• Issued: 04/03/2018
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mrugalski, Grzegorz, Rajski, Janusz, Rybak, Lukasz, Solecki, Jedrzej, Tyszer, Jerzy
• Primary Examiner(s): Britt, Cynthia
• Application Number:
  US15/051,063
• Publication Number:
  US 20160245863A1
• Time in Patent Office: 770 Days
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.

Claims

1. A system, comprising:

a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and

a controller configured at least to output a control signal based on control data stored on chip, outputs of the decompressor being inverted at one or more scan shift clock cycles based on the control signal which enables the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.

2. The system recited in claim 1, further comprising:

a storage medium storing the compressed test patterns and the control data.

3. The system recited in claim 1, further comprising:

a first storage medium storing the compressed test patterns; and

a second storage medium storing the control data.

4. The system recited in claim 1, wherein the outputs of the decompressor are inverted at none of the scan shift clock cycles during the outputting of one of the predetermined number of test patterns.

5. The system recited in claim 1, wherein the outputs of the decompressor are inverted at an output side of the decompressor.

6. The system recited in claim 1, wherein the decompressor comprises a phase-shifter and the outputs of the decompressor are inverted by inverting inputs of the phase shifter.

7. The system recited in claim 6, wherein the decompressor further comprises a ring generator.

8. One or more computer-readable media storing computer-executable instructions for causing a computer or networked computers to perform a method of creating a deterministic built-in self-test system in a circuit design, the method comprising:

generating a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and

generating a controller configured at least to output a control signal based on control data stored on chip, outputs of the decompressor being inverted at one or more scan shift clock cycles based on the control signal which enables the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.

9. The one or more computer-readable media recited in claim 8, wherein the compressed test patterns and the control data are stored on a storage medium.

10. The one or more computer-readable media recited in claim 8, wherein the compressed test patterns are stored on a first storage medium storing and the control data are stored on a second storage medium.

11. The one or more computer-readable media recited in claim 8, wherein the outputs of the decompressor are inverted at none of the scan shift clock cycles during the outputting of one of the predetermined number of test patterns.

12. The one or more computer-readable media recited in claim 8, wherein the outputs of the decompressor are inverted at an output side of the decompressor.

13. The one or more computer-readable media recited in claim 8, wherein the decompressor comprises a phase-shifter and the outputs of the decompressor are inverted by inverting inputs of the phase shifter.

14. The one or more computer-readable media recited in claim 13, wherein the decompressor further comprises a ring generator.

15. A method, executed by at least one processor of a computer, comprising:

generating a cluster of test patterns based on a set of random-pattern-resistant faults, wherein the cluster of test patterns comprises a parent test pattern and a plurality of child test patterns, the parent test pattern being a deterministic and compressible test pattern, each of the plurality of child test patterns being derived by inverting bits of the parent test pattern corresponding to one or more scan shift clock cycles.

16. The method recited in claim 15, wherein the parent test pattern is obtained based on merging test cubes generated for several random-pattern-resistant faults in the set of random-pattern-resistant faults.

17. The method recited in claim 15, wherein the plurality of child test patterns are derived by inverting bits of the parent test pattern in successive scan shift clock cycles and each of the plurality of child test patterns differs from the parent test pattern by bits corresponding to one clock cycle.

18. The method recited in claim 15, further comprising:

generating more clusters of test patterns based on the list of random-pattern-resistant faults; and

performing fault simulation on the cluster of test patterns and the more clusters of test patterns by using the set of random-pattern-resistant faults to determine clusters of effective test patterns.

19. The method recited in claim 15, further comprising:

performing fault simulation on the cluster of test patterns with the set of random-pattern-resistant faults to determine a cluster of effective test patterns;

performing fault simulation on the cluster of effective test patterns with a set of targeted faults to determine a new set of random-pattern-resistant faults and a new set of targeted faults, the set of targeted faults comprising the set of random-pattern-resistant faults and easy-to-detect faults; and

repeating the generating, the performing on the cluster of test patterns and the performing on the cluster of effective test patterns by using the new set of random-pattern-resistant faults to replace the set of random-pattern-resistant faults and using the new set of targeted faults to replace the set of targeted faults.

20. The method recited in claim 15, wherein the set of random-pattern-resistant faults is obtained based on performing fault simulation on a set of pseudo-random test patterns.