Microcontroller architecture for power factor correction converter

• US 9,933,842 B2
• Filed: 04/13/2017
• Issued: 04/03/2018
• Est. Priority Date: 04/15/2016
• Status: Active Grant

• Current Assignee: Copeland Corporation LLC (Emerson Electric Company)
• Original Assignee: Emerson Climate Technologies Incorporated (Emerson Electric Company)
• Inventors: Green, Charles E., Marcinkiewicz, Joseph G.
• Primary Examiner(s): Lou, David S
• Application Number:
  US15/487,426
• Publication Number:
  US 20170300107A1
• Time in Patent Office: 355 Days
• Field of Search: 318729, 318727
• CPC Class Codes: G05B 19/042 using digital processors G05B19/05 takes precedence
• CPC Class Codes: G05B 2219/2614 HVAC, heating, ventillation, climate control
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 8/61 Installation
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 1/327 against abnormal temperatures
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 1/42 Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 1/4291 by using a Buck converter to switch the input current
• CPC Class Codes: H02P 23/26 Power factor control [PFC]
• CPC Class Codes: H02P 29/02 Providing protection against overload without automatic interruption of supply protection against faults of stepper motors H02P8/36
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit for driving a motor of a compressor includes a microcontroller, which includes an op-amp, a comparator, a first serial interface, and a first dedicated pin. The op-amp amplifies a value indicating current in a power factor correction converter, which includes a power switch. The comparator asserts a comparison signal in response to the amplified value exceeding a reference value. The comparison signal is output on the first dedicated pin. A programmable logic device (PLD) includes a second serial interface in communication with the first serial interface and a second dedicated pin. The comparison signal is received on the second dedicated pin and the PLD receives control messages from the microcontroller via the second serial interface. The PLD sets a value in an off-time register based on a control message from the microcontroller. The PLD controls the power switch according to the comparison signal and the off-time register.

Claims

1. A circuit for driving a motor of a compressor, the circuit comprising:

a microcontroller comprising an operational amplifier, a comparator, a first serial interface, and a first dedicated pin, wherein;

the operational amplifier is configured to amplify a value representative of a current in a power factor correction (PFC) converter;

the comparator is configured to compare the amplified value to a reference value and assert a comparison signal in response to the amplified value exceeding the reference value; and

the comparison signal is output on the first dedicated pin;

a programmable logic device comprising a second serial interface in communication with the first serial interface and a second dedicated pin, wherein the comparison signal is received on the second dedicated pin and wherein the programmable logic device is configured to;

receive control messages from the microcontroller via the second serial interface;

in response to receiving a first control message from the microcontroller, set a value in an off-time register based on data in the first control message;

control a power switch of the PFC converter to turn off in response to the comparison signal being asserted;

subsequent to controlling the power switch to turn off, wait for a period of time determined by the off-time register and then control the power switch to turn on;

measure a turn-on delay of the power switch; and

repeat the control, the wait, and the measure.

2. The circuit of claim 1 wherein the programmable logic device is configured to, in response to receiving a second control message from the microcontroller, transmit the measured turn-on delay to the microcontroller.

3. The circuit of claim 2 wherein the programmable logic device is configured to measure a turn-off delay of the power switch.

4. The circuit of claim 3 wherein the programmable logic device is configured to, in response to receiving a third control message from the microcontroller, transmit the measured turn-off delay to the microcontroller.

5. The circuit of claim 1 further comprising a second comparator configured to compare a signal related to a voltage across the power switch to a threshold, wherein the programmable logic device is configured to measure the turn-on delay of the power switch as a delay between controlling the power switch to turn on and receiving an output from the second comparator.

6. The circuit of claim 1 wherein the programmable logic device is configured to:

receive a second control message including a plurality of bits; and

drive the values of the plurality of bits onto a plurality of pins that corresponds one-to-one to the plurality of bits.

7. The circuit of claim 1 wherein the microcontroller is configured to:

receive new firmware via a serial port connected to the microcontroller via the programmable logic device; and

write the new firmware to flash memory that is connected to the microcontroller via the programmable logic device.

8. The circuit of claim 1 wherein the microcontroller is configured to program the programmable logic device using a programming file encoded in a compressed file format, wherein the compressed file format includes serialized instructions that the microcontroller can execute without performing a decompression operation on the programming file.

9. The circuit of claim 1 wherein the programmable logic device includes first and second output pins, and wherein the programmable logic device is configured to toggle the first and second output pins to energize an isolated power supply.

10. The circuit of claim 1 wherein the programmable logic device is configured to directly connect flash programming pins of the microcontroller to flash programming pins of an external flash memory chip.

11. A method of operating a programmable logic device, the method comprising:

incrementing a value in a counter;

comparing the value to a predetermined value, wherein the predetermined value is indicative of a desired off-time of a discrete switching device;

while the value exceeds the predetermined value, generating a control signal that causes the discrete switching device to be energized;

in response to an external input, resetting the value in the counter, wherein the external input indicates that a measured current value corresponding to the discrete switching device has exceeded a threshold current value; and

updating the predetermined value according to a command received by the programmable logic device.

12. The method of claim 11, further comprising generating a clamp control signal while the control signal is not being generated, wherein the clamp control signal prevents the discrete switching device from being energized.

13. The method of claim 12, further comprising halting generation of the clamp control signal while the control signal is being generated.

14. The method of claim 11, further comprising:

receiving a switch state signal that indicates whether the discrete switching device is energized;

in response to a transition in the switch state signal indicating that the discrete switching device has been energized, recording the value of the counter as a turn-on delay; and

storing the turn-on delay.

15. The method of claim 14, further comprising reporting the turn-on delay to a controller external to the programmable logic device.

16. The method of claim 15, further comprising:

receiving a delay request at the programmable logic device over a serial bus; and

transmitting the turn-on delay to a source of the delay request over the serial bus.

17. The method of claim 11, further comprising:

receiving a switch state signal that indicates whether the discrete switching device is energized;

comparing the value of the counter to an acceptable turn-on delay; and

in response to the value of the counter exceeding the acceptable turn-on delay while the switch state signal indicates that the discrete switching device is not energized, generating a fault signal.

18. The method of claim 17, further comprising halting generation of the control signal in response to generation of the fault signal.

19. The method of claim 11, further comprising

receiving a switch state signal that indicates whether the discrete switching device is energized;

in response to a transition in the switch state signal indicating that the discrete switching device has been de-energized, recording the value of the counter as a turn-off delay; and

storing the turn-off delay.

20. A programmable logic device programmed to implement the method of claim 11.