Embedded system boot from a storage device

• US 9,934,045 B1
• Filed: 04/12/2015
• Issued: 04/03/2018
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Manlapat, Alvin Anonuevo, Beleno, Ian Victor Pasion
• Primary Examiner(s): Elamin, Abdelmoniem
• Application Number:
  US14/684,399
• Time in Patent Office: 1,087 Days
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

In an embodiment of the invention, an apparatus comprises an embedded system comprising: a processor configured to execute firmware; a random access memory (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM; a power-on reset (POR) sequencer configured to control a boot process of the embedded system; a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory; a direct memory access (DMA) controller configured initiate and track data transfers; and a configuration and status register (CSR) controller configured to access modules in the embedded system.

Claims

1. An apparatus, comprising:

an embedded system comprising;

a processor configured to execute firmware;

a random access memory (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM;

a power-on reset (POR) sequencer configured to control a boot process of the embedded system, wherein the POR sequence controls the boot process and verifies an integrity of loaded data and code in the RAM;

a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory;

a direct memory access (DMA) controller configured initiate and track data transfers; and

a configuration and status register (CSR) controller configured to provide an interface for the processor to access configuration and status registers of the nonvolatile memory controller, a processor bus, a CSR bus, the DMA controller, and the multi-port memory controller in the embedded system;

wherein the embedded system verifies an integrity of data and code used in the boot process and wherein the embedded system reduces an amount of the nonvolatile memory used in the boot process to provide an advantage in terms of cost and complexity.

2. The apparatus of claim 1, further comprising:

a storage device configured to store data and code.

3. The apparatus of claim 2, wherein the storage device comprises at least one solid state drive (SSD).

4. The apparatus of claim 1, wherein the POR sequencer is configured to signal the nonvolatile memory controller to search for a bootstrap code loader, and wherein the processor is configured to read bootstrap code from the nonvolatile memory;

and

wherein the DMA controller is configured to move firmware from the storage device to the RAM.

5. The apparatus of claim 1, wherein the nonvolatile memory comprises a read only memory (ROM).

6. The apparatus of claim 1, wherein the embedded system further comprises a debug interface configured to pre-program the nonvolatile memory.

7. The apparatus of claim 1, wherein the embedded system further comprises:

a central processing unit (CPU) bus interconnecting the processor, DMA controller, multi-port memory controller, nonvolatile memory controller, and CSR controller; and

the CSR bus interconnecting the DMA controller, multi-port memory controller, nonvolatile memory controller, and CSR controller.

8. The apparatus of claim 1, wherein the processor reads bootstrap code from the nonvolatile memory.

9. The apparatus of claim 1, wherein the processor configures clock sources in the embedded system via the CSR bus.