Fast remote communication and computation between processors using store and load operations on direct core-to-core memory

• US 9,934,079 B2
• Filed: 05/27/2010
• Issued: 04/03/2018
• Est. Priority Date: 05/27/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carter, John Bruce, Elnozahy, Elmootazbellah Nabil, Gheith, Ahmed, Van Hansbergen, Eric, Rajamani, Karthick, Speight, William Evan, Zhang, Lixin
• Primary Examiner(s): Giroux, George
• Application Number:
  US12/789,082
• Publication Number:
  US 20110296138A1
• Time in Patent Office: 2,868 Days
• Field of Search: 712 29
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.

Claims

1. An apparatus for fast remote communication and computation between processors, comprising:

a first processor in a multiprocessor data processing system, the first processor being a remote processor;

a direct core to core communication unit (DCC) configured to operate with the remote processor; and

a memory associated with the DCC,

wherein the memory operates at a hierarchical level of one of (i) level-1 of a processor-cache and (ii) level-2 of the processor-cache in a cache hierarchy of the remote processor,

wherein a first area of the memory is configured as a first address space accessible only to the remote processor and a second area of the memory is configured as a second address space accessible by a second processor in the multiprocessor data processing system,

wherein the second processor gains access to the second area of the memory using an address from the second address space, the memory receiving from the second processor a set of bytes in the second area at the address from the second address space, the set of bytes comprising (i) an operation to be performed at the remote processor and (ii) a context for the operation, wherein the context comprises an encoded reference to an address space of the second processor wherein the reference is used in executing the operation at the remote processor, and

wherein the remote processor executes an operation using the context.

2. The apparatus of claim 1, wherein the encoded reference comprises an effective address in an address space of the second processor.

3. The apparatus of claim 1, wherein the context is a hardware execution context that is created by the remote processor without software intervention.

4. The apparatus of claim 1, wherein the remote processor executes the set of bytes responsive to loading the bytes using a load instruction, wherein the load instruction loads the set of bytes at the remote processor for computation thereby omitting execution of at least one thread for reading the contents of the set of bytes and omitting execution of at least one thread for executing the contents of the set of bytes.

5. The apparatus of claim 1, wherein the remote processor executes the set of bytes responsive to loading the bytes using an instruction that loads the set of bytes at the remote processor for computation without requiring sending an interrupt to the remote processor.

6. The apparatus of claim 1, wherein the remote processor executes the set of bytes responsive to the set of bytes occupying a first logical position in a FIFO queue in the memory.

7. The apparatus of claim 1, wherein the remote processor executes the set of bytes responsive to the set of bytes not being blocked from execution.

8. The apparatus of claim 1, wherein the set of bytes are sent by a thread executing on the second processor.

9. The apparatus of claim 1, wherein the memory is a static random access memory (SRAM).

10. The apparatus of claim 1, wherein the memory is configured to store a plurality of sets of bytes in a first-in first-out (FIFO) queue.

11. The apparatus of claim 1, further comprising:

a first configuration enabling the second processor to write to the memory of the DCC of the remote processor; and

a second configuration configuring the remote processor to allow the second processor to write to the memory of the DCC of the remote processor.

12. The apparatus of claim 1, wherein arrival of the set of bytes in the memory triggers the executing without an interrupt being sent to the remote processor.

13. A computer usable program product comprising a computer usable hardware storage device including computer usable code for fast remote communication and computation between processors, wherein the computer usable code upon execution by a hardware processor causes:

configuring a direct core to core communication unit (DCC) to operate with the processor, the processor being a remote processor;

configuring a first area of a memory associated with the DCC as a first address space accessible only to the remote processor and configuring a second area of the memory as a second address space accessible by a second processor in the multiprocessor data processing system, wherein the memory operates at a hierarchical level of one of (i) level-1 of a processor-cache and (ii) level-2 of the processor-cache in a cache hierarchy of the remote processor, wherein the second processor gains access to the second area of the memory using an address from the second address space;

receiving, from the second processor, at the address from the second address space in the second area of the memory, a set of bytes, the set of bytes comprising (i) an operation to be performed at the remote processor and (ii) a context for the operation, wherein the context comprises an encoded reference to an address space of the second processor wherein the reference is used in executing the operation at the remote processor; and

executing the operation at the remote processor using the context.

14. The computer usable program product of claim 13, wherein the encoded reference comprises an effective address in an address space of the second processor.

15. The computer usable program product of claim 13, wherein the context is a hardware execution context that is created by the remote processor without software intervention.

16. The computer usable program product of claim 13, wherein executing the set of bytes comprises:

loading the bytes using a load instruction, wherein the load instruction loads the set of bytes at the remote processor for computation thereby omitting execution of at least one thread for reading the contents of the set of bytes and omitting execution of at least one thread for executing the contents of the set of bytes.

17. The computer usable program product of claim 13, wherein executing the set of bytes further comprises:

loading the bytes using an instruction that loads the set of bytes at the remote processor for computation without requiring sending an interrupt to the remote processor.

18. The computer usable program product of claim 13, further comprising:

assessing whether the set of bytes is the first in a FIFO queue in the memory, wherein the executing is responsive to the assessing being affirmative.

19. The computer usable program product of claim 13, further comprising:

assessing whether the set of bytes is blocked from execution, wherein the executing is responsive to the assessing being negative.

20. The computer usable program product of claim 13, wherein the set of bytes are sent by a thread executing on the second processor.

21. The computer usable program product of claim 20, further comprising:

composing, using the thread, the set of bytes; and

writing the set of bytes directly to the memory of the DCC of the remote processor.