Fast remote communication and computation between processors using store and load operations on direct core-to-core memory
First Claim
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1. An apparatus for fast remote communication and computation between processors, comprising:
- a first processor in a multiprocessor data processing system, the first processor being a remote processor;
a direct core to core communication unit (DCC) configured to operate with the remote processor; and
a memory associated with the DCC,wherein the memory operates at a hierarchical level of one of (i) level-1 of a processor-cache and (ii) level-2 of the processor-cache in a cache hierarchy of the remote processor,wherein a first area of the memory is configured as a first address space accessible only to the remote processor and a second area of the memory is configured as a second address space accessible by a second processor in the multiprocessor data processing system,wherein the second processor gains access to the second area of the memory using an address from the second address space, the memory receiving from the second processor a set of bytes in the second area at the address from the second address space, the set of bytes comprising (i) an operation to be performed at the remote processor and (ii) a context for the operation, wherein the context comprises an encoded reference to an address space of the second processor wherein the reference is used in executing the operation at the remote processor, andwherein the remote processor executes an operation using the context.
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Abstract
A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
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Citations
21 Claims
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1. An apparatus for fast remote communication and computation between processors, comprising:
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a first processor in a multiprocessor data processing system, the first processor being a remote processor; a direct core to core communication unit (DCC) configured to operate with the remote processor; and a memory associated with the DCC, wherein the memory operates at a hierarchical level of one of (i) level-1 of a processor-cache and (ii) level-2 of the processor-cache in a cache hierarchy of the remote processor, wherein a first area of the memory is configured as a first address space accessible only to the remote processor and a second area of the memory is configured as a second address space accessible by a second processor in the multiprocessor data processing system, wherein the second processor gains access to the second area of the memory using an address from the second address space, the memory receiving from the second processor a set of bytes in the second area at the address from the second address space, the set of bytes comprising (i) an operation to be performed at the remote processor and (ii) a context for the operation, wherein the context comprises an encoded reference to an address space of the second processor wherein the reference is used in executing the operation at the remote processor, and wherein the remote processor executes an operation using the context. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer usable program product comprising a computer usable hardware storage device including computer usable code for fast remote communication and computation between processors, wherein the computer usable code upon execution by a hardware processor causes:
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configuring a direct core to core communication unit (DCC) to operate with the processor, the processor being a remote processor; configuring a first area of a memory associated with the DCC as a first address space accessible only to the remote processor and configuring a second area of the memory as a second address space accessible by a second processor in the multiprocessor data processing system, wherein the memory operates at a hierarchical level of one of (i) level-1 of a processor-cache and (ii) level-2 of the processor-cache in a cache hierarchy of the remote processor, wherein the second processor gains access to the second area of the memory using an address from the second address space; receiving, from the second processor, at the address from the second address space in the second area of the memory, a set of bytes, the set of bytes comprising (i) an operation to be performed at the remote processor and (ii) a context for the operation, wherein the context comprises an encoded reference to an address space of the second processor wherein the reference is used in executing the operation at the remote processor; and executing the operation at the remote processor using the context. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification