Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache

• US 9,934,152 B1
• Filed: 02/17/2016
• Issued: 04/03/2018
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Bryant, Richard, O'Bleness, R. Frank, Jamil, Sujat, Schuttenberg, Kim
• Primary Examiner(s): Bradley, Matthew
• Application Number:
  US15/046,366
• Time in Patent Office: 776 Days
• Field of Search: 711125
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/60 Details of cache memory

Abstract

Systems and techniques relating to hardware alias detection and management in caches are described. A cache controller can receive a cache request that specifies a virtual address, which includes a virtual page number (VPN) and a page offset; access, concurrently, one or more primary tags in a slot of the cache corresponding to a primary cache index that is based on a portion of the page offset and a portion of the VPN and one or more secondary tags in one or more slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the VPN; and determine whether there are any primary or secondary matching ways. The controller can write store data to a primary matching way if it exists and perform an alias management operation if any secondary matching ways exist.

Claims

1. An apparatus comprising:

a cache comprising slots, wherein each of the slots comprises one or more ways and one or more tags; and

a controller coupled with the cache, wherein the controller is configured to;

receive a cache request that specifies a virtual address, the virtual address comprising a virtual page number and a page offset,

access, concurrently, (i) one or more primary tags in a slot of the slots corresponding to a primary cache index that is based on a portion of the page offset and a portion of the virtual page number and (ii) one or more secondary tags in one or more slots of the slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the virtual page number,

determine a physical page number that is associated with the virtual page number,

compare the physical page number to the one or more primary tags to determine whether there is a primary matching way,

compare the physical page number to the one or more secondary tags to determine whether there are one or more secondary matching ways,

if the cache request is associated with a load instruction, return read data from the primary matching way or the one or more secondary matching ways, and

if the cache request is associated with a store instruction, write store data to the primary matching way if it exists and perform an alias management operation if the one or more secondary matching ways exist.

2. The apparatus of claim 1, wherein the alias management operation comprises writing the store data to the one or more secondary matching ways.

3. The apparatus of claim 1, wherein the alias management operation comprises invalidating the one or more secondary matching ways.

4. The apparatus of claim 1, wherein the one or more primary tags and the one or more secondary tags are concurrently compared to the physical page number.

5. The apparatus of claim 1, wherein the controller is further configured to qualify an operation that is responsive to the cache request by checking whether any of the one or more secondary matching ways exist, wherein the one or more secondary tags are compared to the physical page number after the one or more primary tags are compared to the physical page number.

6. The apparatus of claim 1, wherein the portion of the virtual page number includes at least two bits of the virtual page number.

7. The apparatus of claim 1, wherein the cache request is associated with the load instruction, and wherein the controller is configured to return data from the one or more secondary matching ways, if existing, to avoid a cache miss if the primary matching way does not exist.

8. The apparatus of claim 1, wherein the controller is further configured to swap slots to write the store data to avoid an alias condition if the portion of the virtual page number that is used to form the primary cache index changes during address translation.

9. A method comprising:

receiving, at a controller associated with a cache, a cache request that specifies a virtual address, the virtual address comprising a virtual page number and a page offset, the cache comprising slots, wherein each of the slots comprises one or more ways and one or more tags;

accessing, concurrently, (i) one or more primary tags in a slot of the slots corresponding to a primary cache index that is based on a portion of the page offset and a portion of the virtual page number and (ii) one or more secondary tags in one or more slots of the slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the virtual page number;

determining a physical page number that is associated with the virtual page number;

comparing the physical page number to the one or more primary tags to determine whether there is a primary matching way;

comparing the physical page number to the one or more secondary tags to determine whether there are one or more secondary matching ways;

if the cache request is associated with a load instruction, returning read data from the primary matching way or the one or more secondary matching ways; and

if the cache request is associated with a store instruction, writing store data to the primary matching way if it exists and perform an alias management operation if the one or more secondary matching ways exist.

10. The method of claim 9, wherein the alias management operation comprises writing the store data to the one or more secondary matching ways.

11. The method of claim 9, wherein the alias management operation comprises invalidating the one or more secondary matching ways.

12. The method of claim 9, wherein the one or more primary tags and the one or more secondary tags are concurrently compared to the physical page number.

13. The method of claim 9, comprising:

qualifying an operation that is responsive to the cache request by checking whether any of the one or more secondary matching ways exist, wherein the one or more secondary tags are compared to the physical page number after the one or more primary tags are compared to the physical page number.

14. The method of claim 9, wherein the portion of the virtual page number includes at least two bits of the virtual page number.

15. The method of claim 9, wherein the cache request is associated with the load instruction, and wherein the method comprises returning data from the one or more secondary matching ways, if existing, to avoid a cache miss if the primary matching way does not exist.

16. The method of claim 9, comprising:

swapping slots to write the store data to avoid an alias condition if the portion of the virtual page number that is used to form the primary cache index changes during address translation.

17. A system comprising:

a cache comprising slots, wherein each of the slots comprises one or more ways and one or more tags;

circuitry configured to receive a cache request that specifies a virtual address, the virtual address comprising a virtual page number and a page offset;

circuitry configured to access one or more primary tags in a slot of the slots corresponding to a primary cache index that is based on a portion of the page offset and a portion of the virtual page number;

circuitry configured to access one or more secondary tags in one or more slots of the slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the virtual page number;

circuitry configured to compare a physical page number that is associated with the virtual page number to the one or more primary tags to determine whether there is a primary matching way;

circuitry configured to compare the physical page number to the one or more secondary tags to determine whether there are one or more secondary matching ways;

circuitry configured to return, if the cache request is associated with a load instruction, read data from the primary matching way or the one or more secondary matching ways; and

circuitry configured to write, if the cache request is associated with a store instruction, store data to the primary matching way if it exists and perform an alias management operation if the one or more secondary matching ways exist.

18. The system of claim 17, wherein the alias management operation comprises writing the store data to the one or more secondary matching ways.

19. The system of claim 17, wherein the alias management operation comprises invalidating the one or more secondary matching ways.

20. The system of claim 17, wherein the one or more primary tags and the one or more secondary tags are concurrently compared to the physical page number.