Electronic system with memory management mechanism and method of operation thereof
First Claim
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1. An electronic system comprising:
- a processor configured to access operation data;
a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data;
a memory controller, coupled to a buffering cache memory, configured to maintain a flow of the operation data; and
a memory subsystem, coupled to the memory controller, including;
a first tier memory configured to store the operation data, with critical timing, by a fast control bus, anda second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.
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Abstract
An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.
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Citations
15 Claims
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1. An electronic system comprising:
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a processor configured to access operation data; a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to a buffering cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including; a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification