Method, system, and apparatus for page sizing extension
First Claim
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1. A processor, comprising:
- a plurality of execution cores; and
a first translation lookaside buffer (TLB) coupled to the plurality of execution cores, the first TLB to store a first plurality of cached page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and a same format;
a second translation lookaside buffer (TLB) coupled to the plurality of execution cores, the second TLB to store a second plurality of cached page table entries (PTEs), the second plurality of cached PTEs corresponding to memory pages having a different size than the first plurality of cached PTEs of the first TLB, to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and the same format, the format includes;
a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size physical memory pages having corresponding consecutive PTEs are to be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page or larger,a second bit to indicate whether the corresponding memory page has been written,a third bit to indicate whether the corresponding memory page has been accessed, anda fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation.
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Abstract
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
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Citations
14 Claims
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1. A processor, comprising:
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a plurality of execution cores; and a first translation lookaside buffer (TLB) coupled to the plurality of execution cores, the first TLB to store a first plurality of cached page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and a same format; a second translation lookaside buffer (TLB) coupled to the plurality of execution cores, the second TLB to store a second plurality of cached page table entries (PTEs), the second plurality of cached PTEs corresponding to memory pages having a different size than the first plurality of cached PTEs of the first TLB, to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and the same format, the format includes; a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size physical memory pages having corresponding consecutive PTEs are to be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page or larger, a second bit to indicate whether the corresponding memory page has been written, a third bit to indicate whether the corresponding memory page has been accessed, and a fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation. - View Dependent Claims (2, 3, 4, 5)
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6. A system comprising:
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a physical memory to store memory pages including a portion of the memory pages for an operating system; a plurality of execution cores; and a first translation lookaside buffer (TLB) coupled to the plurality of execution cores, the first TLB to store a first plurality of cached page table entries (PTEs) to translate virtual addresses to physical addresses of the memory pages, each PTE having at least 64 bits and a same format; a second translation lookaside buffer (TLB) coupled to the plurality of execution cores, the second TLB to store a second plurality of cached page table entries (PTEs), the second plurality of cached PTEs corresponding to memory pages having a different size than the first plurality of cached PTEs of the first TLB, to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and the same format, the format includes; a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size memory pages can be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page or larger, a second bit to indicate whether the corresponding memory page has been written, a third bit to indicate whether the corresponding memory page has been accessed, and a fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation; said operating system to initialize a memory page of the larger size by initializing a plurality of consecutive PTEs for a corresponding plurality of sequential 4 KB size physical memory pages such that the total memory is the same as the larger size memory page. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A method comprising:
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storing a plurality of page table entries (PTEs) in physical memory to translate virtual addresses to physical addresses of physical memory pages, each PTE having at least 64 bits and a same format and further including; a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size physical memory pages having corresponding consecutive PTEs can be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page, wherein the first single bit to dictate between a first or a second TLB to store the PTE, a second bit to indicate whether the corresponding memory page has been written, a third bit to indicate whether the corresponding memory page has been accessed, and a fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation; initializing a memory page of the larger size by initializing a plurality of consecutive PTEs in physical memory for a corresponding plurality of sequential 4 KB size physical memory pages such that the total physical memory is the same as the larger size memory page; and setting a respective first bit in each of said plurality of consecutive PTEs to indicate whether a respective corresponding memory page is to be treated as a 4-kilobyte (KB) memory page or as a larger size memory page for translating virtual addresses to physical addresses of the respective corresponding memory page. - View Dependent Claims (13, 14)
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Specification