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Method, system, and apparatus for page sizing extension

  • US 9,934,155 B2
  • Filed: 12/20/2012
  • Issued: 04/03/2018
  • Est. Priority Date: 12/31/2007
  • Status: Active Grant
First Claim
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1. A processor, comprising:

  • a plurality of execution cores; and

    a first translation lookaside buffer (TLB) coupled to the plurality of execution cores, the first TLB to store a first plurality of cached page table entries (PTEs) to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and a same format;

    a second translation lookaside buffer (TLB) coupled to the plurality of execution cores, the second TLB to store a second plurality of cached page table entries (PTEs), the second plurality of cached PTEs corresponding to memory pages having a different size than the first plurality of cached PTEs of the first TLB, to translate virtual addresses to physical addresses of memory pages, each PTE having at least 64 bits and the same format, the format includes;

    a first single bit to indicate whether a corresponding memory page is a 4-kilobyte (KB) memory page or a larger size memory page, wherein a plurality of sequential 4 KB size physical memory pages having corresponding consecutive PTEs are to be combined into and treated as the larger size memory page, wherein the first bit is to indicate whether the corresponding memory page is either the 4 KB memory page or a 64 KB memory page or larger,a second bit to indicate whether the corresponding memory page has been written,a third bit to indicate whether the corresponding memory page has been accessed, anda fourth bit to indicate whether the corresponding PTE is able to be used to perform address translation.

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