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Bit-mapped DMA and IOC transfer with dependency table comprising plurality of index fields in the cache for DMA transfer

  • US 9,934,160 B1
  • Filed: 07/22/2016
  • Issued: 04/03/2018
  • Est. Priority Date: 03/15/2013
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory DMA (direct memory access) engine;

    an IOC (input/output to cache) DMA engine;

    a cache;

    a dependency table configured to permit one of the memory DMA engine and IOC DMA engine to transmit data to the cache and to permit, in parallel, another one of the memory DMA engine and IOC DMA engine to drain data from the cache without processor intervention whenever a data buffer in the cache is filled or drained in order to provide a hardware-assisted DMA transfer;

    wherein the dependency table comprises a plurality of index fields, wherein each of the plurality of index fields comprises a plurality of buffer fields;

    wherein the plurality of buffer fields comprises a first buffer field comprising a first plurality of sub-indices assigned to the memory DMA engine;

    wherein the plurality of buffer fields comprises a second buffer field comprising a second plurality of sub-indices assigned to the IOC DMA engine; and

    wherein the cache comprises a first descriptor for the memory DMA engine and a second descriptor for the IOC DMA engine and wherein the first descriptor and the second descriptor point to a first data buffer in the cache.

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