Memory write protection for memory corruption detection architectures

• US 9,934,164 B2
• Filed: 03/16/2017
• Issued: 04/03/2018
• Est. Priority Date: 06/19/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stark, Tomer, Gabor, Ron, Tal, Ady, Nuzman, Joseph
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US15/460,977
• Publication Number:
  US 20170185535A1
• Time in Patent Office: 383 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 2201/80 Database-specific techniques
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1052 Security improvement

Abstract

Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.

Claims

1. A processing system comprising:

a processor core comprising a register to store an address of a memory corruption detection (MCD) table, wherein the processing core is to;

receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory; and

send, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.

2. The processing system of claim 1, wherein the processing core is further to retrieve, from the MCD table, a write protection indicator that indicates the protection mode of the first portion.

3. The processing system of a claim 2, wherein the write protection indicator is a MCD color value.

4. The processing system of a claim 3, wherein the MCD color value is a 6-bit metadata value.

5. The processing system of a claim 2, wherein the memory store request comprises a pointer indicating a first location of the first portion in the memory block to store the data, and wherein the write protection indicator is stored in a bit of the pointer.

6. The processing system of claim 2, wherein the write protection indicator includes a binary code, wherein a first binary number indicates the first portion is write protected and a second binary number indicates that the first portion is non-write protected.

7. The processing system of claim 1, wherein the contiguous memory block comprises the first portion of the contiguous memory block in the protection mode and a second portion of the contiguous memory block in a non-protection mode, wherein the protection mode is a write protection mode and the non-protection mode for the second portion is a non-write protection mode.

8. The processing system of claim 1, wherein the fault event associated with the first portion is an event where the processor core receives, from the application, the memory store request to write data to the first portion.

9. The processing system of claim 1, wherein the first portion stores at least one of allocation metadata, linked-list pointers, or a return address of a function for a stack.

10. The processing system of claim 1, wherein the processing core is further to:

receive, from the application, an allocation request for an allocation of a memory object with the contiguous memory block in the memory;

allocate the contiguous memory block for the memory object in view of a size of the memory object requested; and

write, into the MCD table, a MCD metadata word.

11. The processing system of claim 10, wherein the memory store request comprises:

a first pointer indicating a location of the first portion in the memory block to store the data, wherein the first pointer includes a first MCD unique ID; and

a second pointer indicating a location of the memory object with the contiguous memory block, wherein the second pointer includes a second MCD unique ID, and wherein the processing core is further to write the data to the first portion when the first MCD unique ID matches the second MCD unique ID.

12. The processing system of claim 11, wherein the processing core is further to send the fault message when the first MCD unique ID does not match the second MCD unique ID.

13. A system on a chip (SoC) comprising:

a memory device to store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table; and

a memory controller coupled to the memory device, the memory controller to;

allocate a contiguous memory block in the memory; and

write a MCD word into the MCD table, wherein the MCD word includes a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block, wherein the protection mode indicates that the first portion is write protected.

14. The SoC of claim 13, wherein the MCD word comprises:

a first byte includes a first MCD unique ID and a mode indicator of a second byte; and

the second byte comprises byte level granularity detection information and the write protection indicator.

15. The SoC of claim 13, wherein the memory controller is further to receive, from the application, an allocation request for an allocation of a memory object in the contiguous memory block.

16. The SoC of claim 13, wherein the contiguous memory block comprises:

the first portion of the contiguous memory in the protection mode; and

a second portion of the contiguous memory in a non-protection mode.

17. A processing system comprising:

a processor core comprising a register to store an address of a memory corruption detection (MCD) table, wherein the processing core is to;

write a word into the MCD table, wherein the word comprises a write protection indicator that indicates a protection mode of a first portion of a contiguous memory block in a memory;

receive, from an application, a memory store request to store data in the first portion of the contiguous memory block; and

send, to the application, a fault message when a fault event associated with the first portion occurs in view of the protection mode of the first portion of the contiguous memory block, wherein the protection mode indicates that the first portion is write protected.

18. The processing system of claim 17, wherein the fault event associated with the first portion is an event where the processor core receives, from the application, the memory store request to write data to the first portion.

19. The processing system of claim 17, wherein the contiguous memory block is 64 bytes in size.

20. The processing system of claim 17, wherein the contiguous memory block comprises:

the first portion of the contiguous memory block, wherein the first portion is in a write protection mode; and

a second portion of the contiguous memory block, wherein the second portion is in a non-write protection mode.