Serial communication link with optimal transfer latency
First Claim
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1. A method, comprising:
- for a plurality of signals arranged in a payload such that each signal has a corresponding bit position in the payload, serially transmitting a first frame that identifies the bit position of a changed one of the signals in the payload responsive to a determination that only the changed one of the signals has changed state since the first frame transmission, wherein the first frame does not includes an unchanged remainder of the plurality of signals in the payload; and
subsequent to the second frame transmission, serially transmitting a second frame including the plurality of signals in the payload responsive to a determination that more than one of the signals has changed state since the first frame transmission.
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Abstract
A serial interface is provided with a finite state machine configured to compare a current state for a plurality of signals to a previous state to determine whether to transmit a frame including the plurality of signals or to transmit a frame that includes only a bit position of a changed one of the signals.
9 Citations
20 Claims
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1. A method, comprising:
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for a plurality of signals arranged in a payload such that each signal has a corresponding bit position in the payload, serially transmitting a first frame that identifies the bit position of a changed one of the signals in the payload responsive to a determination that only the changed one of the signals has changed state since the first frame transmission, wherein the first frame does not includes an unchanged remainder of the plurality of signals in the payload; and subsequent to the second frame transmission, serially transmitting a second frame including the plurality of signals in the payload responsive to a determination that more than one of the signals has changed state since the first frame transmission. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit, comprising:
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a processor configured to periodically generate a plurality of signals arranged in a payload from a first signal to a last signal such that each signal in the plurality of signals has a corresponding bit position in the payload; a memory configured to store the plurality of signals from each periodic generation by the processor; and a finite state machine (FSM) configured to compare a current state for the plurality of signals to a previous state for the plurality of signals as retrieved from the memory to determine if only a single one of signals in the current state has changed state compared to the previous state, the FSM being further configured to serially transmit a first frame to a remote processor that identifies an address for the bit position of the single changed signal responsive to the determination that only the single changed signal has changed state. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method, comprising:
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periodically storing a state for a plurality of signals in a memory in a first integrated circuit, wherein the signals are ordered in a sequence from a first signal to a last signal so that each signal has a unique position in the sequence; comparing a current state for the plurality of signals to a previous state for the plurality of signals as retrieved from the memory; responsive to the comparison indicating that more than one of the signals has changed state in the current state, serially transmitting a first frame to a second integrated circuit, wherein the first frame comprises the plurality of signals ordered according to the sequence; and responsive to the comparison indicating that only one of the signals has changed state in the current state and that a remainder of the signals have not changed state, serially transmitting a second frame to the second integrated circuit, wherein the second frame includes an address for the position of the changed signal and does not include the remainder of the signals. - View Dependent Claims (19, 20)
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Specification