Serial communication link with optimal transfer latency

• US 9,934,171 B2
• Filed: 02/10/2016
• Issued: 04/03/2018
• Est. Priority Date: 02/10/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Mishra, Lalan Jee, Wietfeldt, Richard
• Primary Examiner(s): Peyton, Tammara R
• Application Number:
  US15/040,271
• Publication Number:
  US 20170228327A1
• Time in Patent Office: 783 Days
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures

Abstract

A serial interface is provided with a finite state machine configured to compare a current state for a plurality of signals to a previous state to determine whether to transmit a frame including the plurality of signals or to transmit a frame that includes only a bit position of a changed one of the signals.

Claims

1. A method, comprising:

for a plurality of signals arranged in a payload such that each signal has a corresponding bit position in the payload, serially transmitting a first frame that identifies the bit position of a changed one of the signals in the payload responsive to a determination that only the changed one of the signals has changed state since the first frame transmission, wherein the first frame does not includes an unchanged remainder of the plurality of signals in the payload; and

subsequent to the second frame transmission, serially transmitting a second frame including the plurality of signals in the payload responsive to a determination that more than one of the signals has changed state since the first frame transmission.

2. The method of claim 1, wherein serially transmitting the first frame includes serially transmitting a first header and wherein serially transmitting the second frame includes serially transmitting a second header.

3. The method of claim 1, further comprising:

at a general purpose input output (GPIO) interface, receiving a first set of signals from a processor and receiving a second set of GPIO signals from the processor;

from the GPIO interface, transmitting the second set of GPIO signals through corresponding GPIO pins to a remote processor; and

from the GPIO interface, providing in parallel the second set of GPIO signals to a finite state machine (FSM), wherein the second set of GPIO signals comprises the plurality of signals in the payload prior to the transmission of the first frame.

4. The method of claim 3, further comprising:

storing the second set of GPIO signals in a memory;

after the transmission of the first frame, receiving a third set of GPIO signals from the processor at the GPIO interface;

comparing the third set of GPIO signals to the stored second set of GPIO signals to determine that more than one of the GPIO signals has changed state since the transmission of the first frame, wherein serially transmitting the second frame comprises serially transmitting the third set of GPIO signals.

5. The method of claim 3, wherein the serially transmitting the first frame and the second frame is not responsive to an external clock.

6. The method of claim 4, wherein serially transmitting the third set of GPIO signals comprises:

pulse-width-modulating the third set of signals from the GPIO interface into a corresponding series of pulse-width-modulated signals; and

serially transmitting the series of pulse-width-modulated signals through a dedicated transmit pin to the remote processor.

7. The method of claim 1, wherein the payload comprises a byte payload.

8. An integrated circuit, comprising:

a processor configured to periodically generate a plurality of signals arranged in a payload from a first signal to a last signal such that each signal in the plurality of signals has a corresponding bit position in the payload;

a memory configured to store the plurality of signals from each periodic generation by the processor; and

a finite state machine (FSM) configured to compare a current state for the plurality of signals to a previous state for the plurality of signals as retrieved from the memory to determine if only a single one of signals in the current state has changed state compared to the previous state, the FSM being further configured to serially transmit a first frame to a remote processor that identifies an address for the bit position of the single changed signal responsive to the determination that only the single changed signal has changed state.

9. The integrated circuit of claim 8, wherein the FSM is further configured to compare the current state for the plurality of signals to the previous state to determine if more than one of the signals in the current state has changed state compared to the previous state, the FSM being further configured to serially transmit a second frame that includes the plurality of signals to the remote processor responsive to the determination that more than one of the signals has changed state.

10. The integrated circuit of claim 8, wherein the plurality of signals comprises a plurality of first general purpose input output (GPIO) signals.

11. The integrated circuit of claim 10, further comprising:

a dedicated transmit pin;

a plurality of GPIO pins; and

a GPIO interface, wherein the processor is configured to provide a plurality of second GPIO signals to the GPIO interface, and wherein the GPIO interface is configured to transmit the plurality of second GPIO signals to the remote processor through the plurality of GPIO pins, and wherein the FSM is further configured to serially transmit the plurality of first GPIO signals as a plurality of virtual GPIO signals over a dedicated transmit pin to the remote processor.

12. The integrated circuit of claim 9, wherein the FSM is further configured to serially transmit the first frame with a first header and to serially transmit the second frame with a second header.

13. The integrated circuit of claim 12, wherein the first header and the second header are both one-bit signals.

14. The integrated circuit of claim 9, wherein the plurality of signals comprises a pair of bytes, and wherein the FSM is further configured to compare the current state for the plurality of signals to the previous state to determine if only a changed one of the bytes has changed state compared to the previous state, and wherein the FSM is further configured to serially transmit only the changed byte in a third frame to the remote processor responsive to the determination that only the changed byte has changed state.

15. The integrated circuit of claim 11, wherein the FSM is further configured to serially transmit the plurality of virtual GPIO signals as a plurality of pulse-width-modulated signals.

16. The integrated circuit of claim 11, wherein the FSM is further configured to serially transmit the plurality of virtual GPIO signals responsive to cycles of an external clock.

17. The integrated circuit of claim 11, wherein the integrated circuit is included in a system selected from the group consisting of a cellular phone, a smart phone, a personal digital assistant, a tablet computer, a laptop computer, a digital camera, and a handheld gaming device.

18. A method, comprising:

periodically storing a state for a plurality of signals in a memory in a first integrated circuit, wherein the signals are ordered in a sequence from a first signal to a last signal so that each signal has a unique position in the sequence;

comparing a current state for the plurality of signals to a previous state for the plurality of signals as retrieved from the memory;

responsive to the comparison indicating that more than one of the signals has changed state in the current state, serially transmitting a first frame to a second integrated circuit, wherein the first frame comprises the plurality of signals ordered according to the sequence; and

responsive to the comparison indicating that only one of the signals has changed state in the current state and that a remainder of the signals have not changed state, serially transmitting a second frame to the second integrated circuit, wherein the second frame includes an address for the position of the changed signal and does not include the remainder of the signals.

19. The method of claim 18, wherein serially transmitting the second frame further comprises transmitting the changed signal.

20. The method of claim 18, further comprising attaching a first header to the first frame and a second header to the second frame, wherein the first header is different from the second header.