Simulation of modifications to microprocessor design

• US 9,934,341 B2
• Filed: 11/11/2015
• Issued: 04/03/2018
• Est. Priority Date: 11/11/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Berry, Christopher J., Cavitt, Chris A., Matheny, Adam P., Neves, Jose L., Surprise, Jesse P., Wood, Michael H.
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/937,903
• Publication Number:
  US 20170132340A1
• Time in Patent Office: 874 Days
• Field of Search: 716108, 716113, 716134, 703 16, 714 34, 714732, 714741
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Claims

1. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to:

identify an open path in a microprocessor design;

simulate at least one modification to a design of the open path, wherein simulating the at least one modification comprises accepting as true an updated property of the open path based on an estimated effect that would result from a design of the at least one modification;

calculate an updated arrival time at a first pin based on the at least one simulated modification;

calculate an updated path time based on the updated arrival time; and

determine, based on the updated path time, whether the open path would remain open if the at least one simulated modification were designed into the open path;

wherein the microprocessor design is modified based on the determination;

wherein the computer readable storage medium is not transitory per se.

2. The computer program product of claim 1 wherein causing the computer to accept as true an updated property of the open path comprises:

simulating an integration distance reduction to the open path, comprising;

identifying a first net on the open path;

identifying a beginning point of the net and an ending point of the net;

identifying an integration distance for the net;

identifying a modified Manhattan Distance between the beginning point and ending point; and

substituting the modified Manhattan Distance for the integration distance;

simulating an integration-speed substitution to a second net on the path, comprising;

identifying the second net on the open path;

identifying a first layer on which the second net is located;

identifying an integration speed of a second layer, wherein the integration speed of the second layer is different from an integration speed of the first layer; and

substituting the integration speed of the second layer for the integration speed of the first layer over the net;

simulating a decrease to a rise/fall time on a pin, comprising;

identifying a pin on the path based on the potential of a long rise/fall time at the pin; and

applying a shorter rise/fall time at the pin.

3. The computer program product of claim 1, wherein the updated property comprises an updated integration distance of a net on the open path.

4. The computer program product of claim 1, wherein the updated property comprises an updated integration speed of a net on the open path.

5. The computer program product of claim 1, wherein the updated property comprises an updated rise/fall time on a pin on the open path.

6. A system comprising one or more computer processor circuits configured to perform a method comprising:

identifying an open path in a microprocessor design;

simulating at least one modification to a design of the open path, wherein simulating the at least one modification comprises accepting as true an updated property of the open path based on an estimated effect that would result from a design of the at least one modification;

calculating an updated arrival time at a first pin based on the at least one simulated modification;

calculating an updated path time based on the updated arrival time; and

determining, based on the updated path time, whether the open path would remain open if the at least one simulated modification were designed into the open path;

wherein the microprocessor design is modified based on the determination.

7. The system of claim 6 wherein accepting as true an updated property of the open path comprises:

simulating an integration distance reduction to the open path, comprising;

identifying a net on the open path;

identifying a beginning point of the net and an ending point of the net;

identifying an integration distance for the net;

identifying a modified Manhattan Distance between the beginning point and ending point; and

substituting the modified Manhattan Distance for the integration distance;

simulating an integration-speed substitution to the net on the path, comprising;

identifying a first layer on which the net is located;

identifying an integration speed of a second layer, wherein the integration speed of the second layer is different than an integration speed of the first layer; and

substituting the integration speed of the second layer for the integration speed of the first layer over the net;

simulating a decrease to a rise/fall time on a pin, comprising;

identifying a pin on the path based on the potential of a long rise/fall time at the pin; and

applying a shorter rise/fall time at the pin.

8. The system of claim 6, wherein the updated property comprises an updated integration distance of a net on the open path.

9. The system of claim 6, wherein the updated property comprises an updated integration speed of a net on the open path.

10. The system of claim 6, wherein the updated property comprises an updated rise/fall time on a pin on the open path.