Pattern selection for full-chip source and mask optimization

• US 9,934,350 B2
• Filed: 10/02/2015
• Issued: 04/03/2018
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Liu, Hua-Yu
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US14/874,134
• Publication Number:
  US 20160026750A1
• Time in Patent Office: 914 Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 7/70441 Optical proximity correction [OPC]
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Claims

1. A method of configuring a lithographic process of imaging a portion of a design layout onto a substrate, the method comprising:

evaluating, by a hardware computer system, a lithographic process performance of a set of patterns from the portion of the design layout in conjunction with an illumination configuration;

based on the evaluated performance, identifying at least one of the patterns as a potential hot spot that has a process window limiting effect for the lithographic process; and

modifying, by the computer system, the illumination configuration and/or the portion of the design layout based on a subset of the patterns, the subset including the at least one pattern identified as a potential hotspot.

2. The method of claim 1, wherein evaluating the lithographic process performance and/or modifying the illumination configuration and/or the portion of the design layout, comprises simulating the lithographic process using a model of the lithographic process and one or more of the patterns.

3. The method of claim 1, wherein evaluating the lithographic performance comprises determining whether each pattern of the set of patterns will print within a desired process window for the lithographic process.

4. The method of claim 3, wherein the desired process window comprises a parameter of exposure latitude and/or depth of focus.

5. The method of claim 1, wherein the portion of the design layout comprises a full chip.

6. The method of claim 1, wherein identifying at least one of the patterns as a potential hot spot further comprises:

calculating a severity score for a potential hot spot; and

selecting the potential hot spot having a predefined severity score or selecting the hot spot having a severity score within a predefined severity score range.

7. The method of claim 1, wherein identifying at least one of the patterns as a potential hot spot comprises evaluating edge placement error and/or mask error enhancement factor of the patterns.

8. The method of claim 1, further comprising evaluating, by a computer system, lithographic process performance of the modified illumination configuration and/or portion of the design layout and based on the evaluated performance of the modified illumination configuration and/or portion of the design layout, identifying at least one further pattern as a potential hot spot, and modifying the illumination configuration and/or the portion of the design layout based on at least the further pattern.

9. The method of claim 1, further comprising, prior to the evaluating the lithographic process performance of the set of patterns:

evaluating, by a computer system, lithographic process performance of a full set of clips for the portion of the design layout;

based on the evaluated performance of the full set of clips, identifying at least one of the clips as a potential hot spot; and

modifying, by the computer system, an illumination configuration and/or the portion of the design layout based on a subset of the clips, the subset including the at least one clip identified as a potential hotspot,

wherein the set of patterns comprises the full set of clips.

10. The method of claim 1, further comprising verifying the manufacturability of the subset of patterns in conjunction with the modified illumination configuration and/or portion of the design layout.

11. The method of claim 1, further comprising:

using a simulation model of the lithographic process to estimate process parameter sensitivities for each pattern of the set of patterns; and

selecting at least one pattern for inclusion in the subset based on the estimated process parameter sensitivities.

12. The method of claim 1, comprising modifying the portion of the design layout, wherein modifying the portion of the design layout comprises performing optical proximity correction on certain of the patterns of the portion of the design layout and/or placing sub-resolution assist features within the portion of the design layout.

13. The method of claim 1, comprising modifying the portion of the design layout to optimize the portion of the design layout with the illumination configuration or a modified illumination configuration.

14. A patterning device structure configured to impart a pattern to a radiation beam from an illumination system of a lithographic apparatus that is configured to project the radiation beam with the imparted pattern via a projection system onto a target portion of a substrate, wherein the patterning device structure comprises an optimized portion of a design layout, the optimized portion determined by the method of claim 13.

15. A computer program product comprising a non-transitory computer readable medium having instructions thereon, the instructions, when executed by a computer system, implement the method of claim 1.

16. A method of configuring a lithographic process of imaging a portion of a design layout onto a substrate, the method comprising:

obtaining a full set of clips from the portion of the design layout;

identifying, by a hardware computer system, at least one clip from the full set of the clips as a potential hot spot that has a process window limiting effect for the lithographic process, based on a lithographic process performance of the full set of clips; and

optimizing, by the hardware computer system, an illumination configuration and/or the portion of the design layout based on a subset of the full set of clips, the subset including the at least one clip identified as a potential hotspot.

17. The method of claim 16, wherein the identifying and/or the optimizing, comprises simulating the lithographic process using a model of the lithographic process and one or more of the clips.

18. The method of claim 16, wherein the identifying comprises determining whether each clip of the full set of clips will print within a desired process window for the lithographic process.

19. The method of claim 16, wherein identifying at least one clip as a potential hot spot further comprises:

calculating a severity score for a potential hot spot; and

selecting the potential hot spot having a predefined severity score or selecting the hot spot having a severity score within a predefined severity score range.

20. A computer program product comprising a non-transitory computer readable medium having instructions thereon, the instructions, when executed by a computer system, implement the method of claim 16.