Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design
First Claim
1. A computer implemented method for implementing a layout-driven, multi-fabric schematic design of an electronic design, the computer implemented method comprising:
- identifying, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information;
correlating a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and
generating a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information.
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Abstract
Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.
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Citations
20 Claims
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1. A computer implemented method for implementing a layout-driven, multi-fabric schematic design of an electronic design, the computer implemented method comprising:
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identifying, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information; correlating a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and generating a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system for implementing a layout-driven, multi-fabric schematic design of an electronic design, the system comprising:
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a plurality of modules, at least one of which comprises at least one microprocessor including one or more processor cores executing one or more threads in a computing system; and a non-transitory computer accessible storage medium storing thereupon a program code that includes a sequence of instructions that, when executed by the at least one micro-processor or processor core of a computing system, causes the at least one micro-processor or processor core at least to; identify, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information; correlate a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and generate a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information. - View Dependent Claims (14, 15, 16)
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17. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing a layout-driven, multi-fabric schematic design of an electronic design, the set of acts comprising:
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identifying, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information; correlating a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and generating a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information. - View Dependent Claims (18, 19, 20)
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Specification