Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

• US 9,934,354 B1
• Filed: 07/08/2016
• Issued: 04/03/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Kukal, Taranjit Singh, Singh, Balvinder, Durrill, Steven R., Ginetti, Arnold, Khanna, Vikrant, Dabral, Abhishek, Sharma, Madhur, Gupta, Nikhil, Bhattacharya, Ritabrata
• Primary Examiner(s): Lin, Sun
• Application Number:
  US15/205,593
• Time in Patent Office: 634 Days
• Field of Search: 716110, 716111, 716112
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Claims

1. A computer implemented method for implementing a layout-driven, multi-fabric schematic design of an electronic design, the computer implemented method comprising:

identifying, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information;

correlating a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and

generating a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information.

2. The computer implemented method of claim 1, further comprising:

modifying the multi-fabric schematic based in part or in whole upon results of verifications or analyses performed on the multi-fabric schematic.

3. The computer implemented method of claim 1, further comprising:

identifying a first device from the first set of devices in the multi-fabric layout;

determining the layout connectivity information for the first device from the layout connectivity information; and

identifying a first parasitic model based in part or in whole upon the device map.

4. The computer implemented method of claim 3, wherein the multiple design fabrics include two of an integrated circuit (IC) design fabric, an IC package design fabric, and a printed circuit board (PCB) design fabric.

5. The computer implemented method of claim 3, further comprising:

an act of parsing the first parasitic model; and

retrieving header information from the first parasitic model based in part or in whole upon results of the act of parsing the first parasitic model.

6. The computer implemented method of claim 3, further comprising:

instantiating a first parasitic model instance of the first parasitic model in the multi-fabric schematic; and

determining a first number of ports, first port ordering, and first identifications of the first number of ports for the first parasitic model instance of the first parasitic model in the multi-fabric schematic based in part or in whole upon information in the first parasitic model or the layout connectivity information; and

incorporating the first number of ports, the first port ordering, and the first identifications of the number of ports into the first parasitic model instance.

7. The computer implemented method of claim 6, further comprising:

identifying a second set of devices that corresponds to no available parasitic models for representing the second set of devices in the multi-fabric schematic; and

identifying a second device from the second set of devices.

8. The computer implemented method of claim 7, further comprising:

representing the second device from the second set of devices as a conventional schematic instance; and

augmenting the conventional schematic instance with a second number of ports, second port ordering, and second identifications of the second number of ports for the second device.

9. The computer implemented method of claim 7, further comprising:

constructing a second parasitic model for the second device from the second set of devices; and

instantiating a second parasitic model instance of the second parasitic model to represent the second device in the multi-fabric schematic, the second parasitic model instance including a second number of ports, second port ordering, and second identifications of the second number of ports for the second device.

10. The computer implemented method of claim 6, further comprising:

determining routing between a plurality of instances in the multi-fabric schematic;

identifying a third schematic instance of a third device from the multi-fabric schematic;

determining a third parasitic model instance for the third device;

replacing the third schematic instance with the third parasitic model instance; and

updating the device map to modify binding information for the third device.

11. The computer implemented method of claim 6, further comprising:

implementing one or more modifications to the multi-fabric schematic or multi-fabric layout; and

synchronizing the multi-fabric layout, the multi-fabric schematic, and the device map based in part or in whole upon the one or more modifications.

12. The computer implemented method of claim 11, further comprising:

an act of performing one or more verification tasks on the multi-fabric schematic, the one or more verification tasks including a layout-versus-schematic check; and

reporting one or more differences identified from the one or more verification tasks based in part or in whole upon results of the act of performing the one or more verification tasks.

13. A system for implementing a layout-driven, multi-fabric schematic design of an electronic design, the system comprising:

a plurality of modules, at least one of which comprises at least one microprocessor including one or more processor cores executing one or more threads in a computing system; and

a non-transitory computer accessible storage medium storing thereupon a program code that includes a sequence of instructions that, when executed by the at least one micro-processor or processor core of a computing system, causes the at least one micro-processor or processor core at least to;

identify, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information;

correlate a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and

generate a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information.

14. The system of claim 13, wherein the program code includes the sequence of instructions that, when executed by the at least one micro-processor or processor core, further causes the at least one processor or processor core to:

identify a first device from the first set of devices in the multi-fabric layout;

determine the layout connectivity information for the first device from the layout connectivity information; and

identify a first parasitic model based in part or in whole upon the device map.

15. The system of claim 14, wherein the program code includes the sequence of instructions that, when executed by the at least one micro-processor or processor core, further causes the at least one processor or processor core to:

instantiate a first parasitic model instance of the first parasitic model in the multi-fabric schematic; and

determine a first number of ports, first port ordering, and first identifications of the first number of ports for the first parasitic model instance of the first parasitic model in the multi-fabric schematic based in part or in whole upon information in the first parasitic model or the layout connectivity information; and

incorporate the first number of ports, the first port ordering, and the first identifications of the number of ports into the first parasitic model instance.

16. The system of claim 15, wherein the program code includes the sequence of instructions that, when executed by the at least one micro-processor or processor core, further causes the at least one processor or processor core to:

identify a second set of devices that corresponds to no available parasitic models for representing the second set of devices in the multi-fabric schematic;

identify a second device from the second set of devices;

represent the second device from the second set of devices as a conventional schematic instance; and

augment the conventional schematic instance with a second number of ports, second port ordering, and second identifications of the second number of ports for the second device.

17. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for implementing a layout-driven, multi-fabric schematic design of an electronic design, the set of acts comprising:

identifying, with a multi-fabric implementation module including or coupled with at least one micro-processor of a computing system, a multi-fabric layout spanning across multiple design fabrics and layout connectivity information;

correlating a first set of devices in the multi-fabric layout with respective parasitic models at least by referencing a device map corresponding to the multi-fabric layout; and

generating a multi-fabric schematic by using at least the respective parasitic models and the layout connectivity information.

18. The article of manufacture of claim 17, the set of acts further comprising:

identifying a first device from the first set of devices in the multi-fabric layout;

determining the layout connectivity information for the first device from the layout connectivity information; and

identifying a first parasitic model based in part or in whole upon the device map, wherein the multiple design fabrics include two of an integrated circuit (IC) design fabric, an IC package design fabric, and a printed circuit board (PCB) design fabric.

19. The article of manufacture of claim 18, the set of acts further comprising:

instantiating a first parasitic model instance of the first parasitic model in the multi-fabric schematic; and

determining a first number of ports, first port ordering, and first identifications of the first number of ports for the first parasitic model instance of the first parasitic model in the multi-fabric schematic based in part or in whole upon information in the first parasitic model or the layout connectivity information;

incorporating the first number of ports, the first port ordering, and the first identifications of the number of ports into the first parasitic model instance;

identifying a second set of devices that corresponds to no available parasitic models for representing the second set of devices in the multi-fabric schematic; and

identifying a second device from the second set of devices.

20. The article of manufacture of claim 19, the set of acts further comprising:

constructing a second parasitic model for the second device from the second set of devices; and

instantiating a second parasitic model instance of the second parasitic model to represent the second device in the multi-fabric schematic, the second parasitic model instance including a second number of ports, second port ordering, and second identifications of the second number of ports for the second device.