Neuromorphic computational system(s) using resistive synaptic devices

• US 9,934,463 B2
• Filed: 05/16/2016
• Issued: 04/03/2018
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Seo, Jae-sun, Yu, Shimeng, Cao, Yu, Vrudhula, Sarma
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US15/156,113
• Publication Number:
  US 20160336064A1
• Time in Patent Office: 687 Days
• Field of Search: 365148, 365 63, 365174, 365163
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods

Abstract

Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

Claims

1. Computational circuitry comprising:

a cross point resistive network comprising conductive lines and variable resistive units coupled to the conductive lines such that the conductive lines and the variable resistive units form the cross point resistive network; and

control circuitry coupled to the cross point resistive network and configured to;

provide a potential across a first plurality of the variable resistive units such that the first plurality of the variable resistive units provides a line current;

provide the potential across a second plurality of the variable resistive units such that the second plurality of the variable resistive units provides a correction line current; and

calculate a corrected line current by subtracting the correction line current from the line current.

2. The computational circuitry of claim 1 wherein:

the cross point resistive network is arranged such that the variable resistive units are arranged in columns of the variable resistive units;

the first plurality of the variable resistive units is a first column of the columns of the variable resistive units; and

the second plurality of the variable resistive units is a second column of the columns of the variable resistive units.

3. The computational circuitry of claim 2 wherein:

each of the variable resistive units is configured to provide a variable conductance; and

the variable conductance of each of the second plurality of the variable resistive units is provided in a minimum conductance state.

4. The computational circuitry of claim 3 wherein the variable conductance of each of the variable resistive units may be set to a plurality of conductance states between the minimum conductance state and a maximum conductance state.

5. The computational circuitry of claim 4 wherein the control circuitry is configured to set the variable conductance of each of the variable resistive units such that each of the variable resistive units represents a matrix value in a matrix.

6. The computational circuitry of claim 5 wherein the control circuitry is configured to set the variable conductance of each of the variable resistive units by providing at least one positive voltage pulse and at least one negative voltage pulse across each of the variable resistive units.

7. The computational circuitry of claim 6 wherein the at least one positive voltage pulse has a longer pulse duration than the at least one negative voltage pulse and the at least one positive voltage pulse has a voltage magnitude that is greater than a voltage magnitude of the at least one negative voltage pulse.

8. The computational circuitry of claim 6 wherein the at least one negative voltage pulse has a longer pulse duration than the at least one positive voltage pulse and the at least one negative voltage pulse has a voltage magnitude that is greater than a voltage magnitude of the at least one positive voltage pulse.

9. The computational circuitry of claim 5 wherein the control circuitry is configured to set the variable conductance of each of the variable resistive units by providing a plurality of voltage pulses across each of the variable resistive units, wherein a pulse duration of each of the plurality of voltage pulses depends on the conductance state.

10. The computational circuitry of claim 1 wherein a cross point resistive array comprises variable resistive elements such that the variable resistive units are each provided as a subarray of the variable resistive elements.

11. The computational circuitry of claim 1 wherein a cross point resistive array comprises variable resistive elements and wherein the cross point resistive array is configured such that the variable resistive units are reconfigurable such that each of the variable resistive units are reconfigurable to be different combinations of the variable resistive elements.