SRAM cell with dynamic split ground and split wordline
First Claim
1. A memory cell, comprising:
- cross coupled inverters comprising PFETs and NFETs;
a bitline left (BL) which accesses a first inverter of cross coupled inverters by enabling a first access transistor;
a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor;
a wordline left (WL) with enables the first access transistor;
a wordline right (WR) which enables the second access transistor; and
a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,wherein GNDL and GNDR are kept common.
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Accused Products
Abstract
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
21 Citations
10 Claims
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1. A memory cell, comprising:
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cross coupled inverters comprising PFETs and NFETs; a bitline left (BL) which accesses a first inverter of cross coupled inverters by enabling a first access transistor; a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor; a wordline left (WL) with enables the first access transistor; a wordline right (WR) which enables the second access transistor; and a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters, wherein GNDL and GNDR are kept common. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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- 9. A read operation of a memory cell, comprising enabling a first transistor of an asymmetric memory cell to allow access of a first bitline to a storage cell, while raising or lowering a vertical ground line of two separated ground lines connected to transistors of the storage cell above or below ground, GND.
Specification