Memory device with defined programming transaction time

• US 9,934,866 B2
• Filed: 02/18/2015
• Issued: 04/03/2018
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Haukness, Brent, Shaeffer, Ian
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US14/625,505
• Publication Number:
  US 20150162092A1
• Time in Patent Office: 1,140 Days
• Field of Search: 711103, 711167
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

Claims

1. A memory device, comprising:

memory cells in a memory array;

logic to hold a received value representing a programmably-defined memory transaction time, defined according to a calibration operation performed on memory cells of the memory array, the programmably-defined memory transaction time corresponding to a maximum time expected for correct programming of data into memory cells of the memory array; and

logic to compare the programmably-defined memory transaction time with time consumed by a write operation in the memory array, and to generate a signal state for provision to a memory controller, wherein the signal state indicates whether the write operation has resulted in correct programming of data into memory cells of the memory array within the programmably-defined memory transaction time.

2. The memory device of claim 1, wherein:

the memory device further comprises circuitry to receive and process an instruction from the memory controller to perform a transaction upon the memory cells;

the instruction is to convey the received value to the logic to compare; and

the signal state is to indicate whether the write operation has resulted in correct programming of data specified by the instruction into the memory cells within the memory array within the programmably-defined memory transaction time also conveyed by the instruction via the received value.

3. The memory device of claim 1, further comprising a pin by which to unsolicitedly output the signal state to the memory controller.

4. The memory device of claim 3, embodied as a flash memory device, wherein the memory cells are flash memory cells, and wherein the logic to compare is to compare the programmably-defined memory transaction time with time consumed by correct programming of a minimum unit of a page of information into a page of memory cells serviced by a common word line in the memory array.

5. The memory device of claim 1, wherein:

the logic to hold the received value is to hold received values, including one respective to each of mutually-exclusive subdivisions of the memory array, each received value corresponding to a maximum time expected for correct programming of data into memory cells of a corresponding one of the mutually-exclusive subdivisions of the memory array;

the logic to compare the programmably-defined memory transaction time with time consumed by the write operation in the memory array is to compare the programmably-defined memory transaction time respective to a particular one of the mutually-exclusive subdivisions of the memory array with time consumed by a write operation directed to the particular one of the mutually-exclusive subdivisions in the memory array; and

the signal state indicates whether the write operation directed to the particular one has resulted in correct programming of data into memory cells corresponding to the particular one within the programmably-defined memory transaction time respective to the particular one.

6. The memory device of claim 1, wherein:

the memory device further comprises a mode register to store a programmably-defined mode;

the memory device is to use the programmably-defined transaction time in dependence on the programmably-defined mode; and

at least one possible value for programmably-defined mode stored in said mode register is to cause the memory device to alert the memory controller if the write operation has not completed within the programmably-defined memory transaction time.

7. The memory device of claim 1, wherein:

the memory device is to store multiple programmably-defined memory transaction times; and

said memory device is to utilize said multiple programmably-defined memory transaction times in assessing proper performance of the memory cells of the memory array in changing logic state.

8. A memory device, comprising:

memory locations in a non-volatile memory array, each memory location characterized by a programming time that is expected to change over a lifetime of the memory device;

logic to hold a received value representing a programmably-defined memory transaction time that corresponds to a maximum expected time for proper programming of data into one or more of the memory locations of the non-volatile memory array; and

logic to compare the programmably-defined memory transaction time with time consumed by a write operation directed to the one or more of the memory locations, and to generate a signal for provision to a memory controller to indicate whether the write operation has resulted in correct programming of data into the one or more of the memory locations within the programmably-defined memory transaction time.

9. The memory device of claim 8, wherein:

the memory device further comprises circuitry to receive and process an instruction from the memory controller to perform a transaction upon one of the memory locations;

the instruction is to convey the received value to the logic to compare; and

the signal is to indicate whether the write operation has resulted in correct programming of data specified by the instruction into the one of the memory locations within the programmably-defined memory transaction time also conveyed by the instruction via the received value.

10. The memory device of claim 8, further comprising a pin by which to unsolicitedly output the signal to the memory controller.

11. The memory device of claim 8, embodied as a flash memory device, wherein each of the memory locations comprises at least a page of flash memory cells, and wherein the logic to compare is to compare the programmably-defined memory transaction time with time consumed by correct programming of a minimum unit of a page of information into a page of memory cells serviced by a common word line in the non-volatile memory array.

12. The memory device of claim 8, wherein:

the logic to hold the received value is to hold received values, including one respective to each of mutually-exclusive subdivisions of the non-volatile memory array, each of the mutually-exclusive subdivisions comprising at least one of the memory locations, each received value corresponding to a maximum time expected for correct programming of data into memory cells of a corresponding one of the mutually-exclusive subdivisions of the non-volatile memory array; and

the logic to compare the programmably-defined memory transaction time with time consumed by the write operation in the non-volatile memory array is to compare the programmably-defined memory transaction time respective to a particular one of the mutually-exclusive subdivisions of the non-volatile memory array with time consumed by a write operation directed to the particular one of the mutually-exclusive subdivisions in the non-volatile memory array, wherein the signal indicates whether the write operation directed to the particular one has resulted in correct programming of data into memory cells corresponding to the particular one within the programmably-defined memory transaction time respective to the particular one.

13. The memory device of claim 8, wherein:

the memory device further comprises a mode register to store a programmably-defined mode; and

the memory device is to use the programmably-defined transaction time in dependence on the programmably-defined mode;

at least one possible value for programmably-defined mode stored in said mode register is to cause the memory device to notify the memory controller if the write operation has not completed within the programmably-defined memory transaction time.

14. The memory device of claim 8, wherein:

the memory device is to store multiple programmably-defined memory transaction times; and

said memory device is to utilize said multiple programmably-defined memory transaction times in assessing proper performance of memory cells of each memory location in the non-volatile memory array in changing logic state.

15. A memory device, comprising:

logic to receive from a memory controller a programmably-defined value representing an expected maximum write time for a non-volatile memory location of the memory device;

logic to compare write data received as part of a write operation directed to the non-volatile memory location with content of the non-volatile memory location following the write operation, to test for proper programming of the non-volatile memory location and to determine whether proper programming has been effected;

logic to obtain a measure of time consumed by proper programming pursuant to the write operation and to compare the measure with the programmably-defined value;

logic to notify the memory controller if the expected maximum write time is reached without proper programming pursuant to the write operation.

16. The memory device of claim 15, wherein:

the memory device further comprises circuitry to receive and process an instruction from the memory controller to perform a transaction upon the non-volatile memory location;

the instruction is to convey the programmably-defined value to the logic to obtain and compare; and

the memory device is to notify the memory controller if the expected maximum write time is reached without correct programming into the non-volatile memory location of data specified by the instruction according to the programmably-defined value also conveyed by the instruction.

17. The memory device of claim 15, embodied as a flash memory device, wherein the non-volatile memory location comprises flash memory cells, and wherein the logic to obtain and compare is to compare the programmably-defined value with time consumed by correct programming of a minimum unit of a page of information into a page of memory cells serviced by a common word line in the memory device, wherein further, the logic to notify is to transmit an error signal to the memory controller in event that the expected maximum write time is reached without proper programming pursuant to the write operation.

18. The memory device of claim 15, wherein:

the memory device comprises non-volatile storage to received values, including one respective to each of mutually-exclusive subdivisions of the memory device, each received value corresponding to a maximum time expected for correct programming of data into memory cells of a corresponding one of the mutually-exclusive subdivisions of the memory array; and

the logic to compare the programmably-defined value with time consumed by proper programming is to compare the received value respective to a particular one of the mutually-exclusive subdivisions of the memory device with time consumed by a write operation directed to the particular one of the mutually-exclusive subdivisions in the memory device, wherein the logic to notify is to indicate to the memory controller whether the write operation directed to the particular one has resulted in correct programming of data into memory cells corresponding to the particular one within a programmably-defined maximum transaction time respective to the particular one.

19. The memory device of claim 15, wherein:

the memory device is to store multiple programmably-defined memory transaction times; and

said memory device is to utilize said multiple programmably-defined memory transaction times in assessing proper performance of memory cells of the memory device in changing logic state.

20. The memory device of claim 15, wherein the logic to obtain the measure and to compare the measure with the programmably-defined value is to do so for plural ensuing write operations directed to respective non-volatile memory locations of the memory device.