Methods of forming vertical transistor devices with different effective gate lengths

• US 9,935,018 B1
• Filed: 02/17/2017
• Issued: 04/03/2018
• Est. Priority Date: 02/17/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Yeh, Chun-Chen, Yamashita, Tenko, Cheng, Kangguo
• Primary Examiner(s): Yushin, Nikolay
• Application Number:
  US15/436,281
• Time in Patent Office: 410 Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

One illustrative method disclosed herein includes, among other things, forming first and second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and second vertical transistor devices, and forming first and second top spacers, respectively, around the first and second VOC structures, wherein the first spacer thickness is greater than the second spacer thickness. In this example, the method also includes performing at least one epitaxial deposition process to form a first top source/drain structure around the first VOC structure and above the first top spacer and a second top source/drain structure around the second VOC structure and above the second top spacer, and performing an anneal process so as to cause dopants in the first and second doped top source/drain structures to migrate into, respectively, the first and second VOC structures.

Claims

1. A method comprising:

forming a first and a second vertically-oriented channel semiconductor structure for, respectively, a first and a second vertical transistor device above a semiconductor substrate;

forming a first and a second top spacer, respectively, around said first and second vertically-oriented channel semiconductor structures, said first and second top spacers having, respectively, a first and a second spacer thickness, wherein said first spacer thickness is greater than said second spacer thickness;

performing at least one epitaxial deposition process to form;

a first doped top source/drain structure around said first vertically-oriented channel semiconductor structure and above said first top spacer; and

a second doped top source/drain structure around said second vertically-oriented channel semiconductor structure and above said second top spacer; and

performing an anneal process so as to cause;

dopant atoms in said first doped top source/drain structure to migrate into said first vertically-oriented channel semiconductor structure; and

dopant atoms in said second doped top source/drain structure to migrate into said second vertically-oriented channel semiconductor structure.

2. The method of claim 1, wherein said first vertical transistor device and said second vertical transistor device are opposite type devices.

3. The method of claim 1, wherein forming said first and said second top spacer comprises:

performing a first deposition process to form a first layer of top spacer material comprising a first spacer material for both said first and second vertical transistor devices;

performing a second deposition process to form a second layer of top spacer material comprising a second spacer material on said first layer of top spacer material, wherein said second spacer material is a different material than said first spacer material;

forming a patterned etch mask above said second layer of top spacer material that exposes a portion of said second layer of top spacer material; and

performing a selective etching process through said patterned etch mask to selectively remove said exposed portion of said second layer of top spacer material relative to said first layer of top spacer material, wherein said first top spacer comprises said first layer of top spacer material and said second layer of top spacer material and said second top spacer comprises said first layer of top spacer material.

4. The method of claim 1, wherein forming said first and said second top spacer comprises:

performing a first deposition process to form a first layer of top spacer material for both said first and second vertical transistor devices;

forming a patterned etch mask above said first layer of top spacer material that exposes a portion of said first layer of top spacer material for said second vertical transistor device;

performing an etching process through said patterned etch mask to selectively remove said exposed portion of said first layer of top spacer material for said second vertical transistor device and thereby leave a remaining portion of said first layer of top spacer material for said first vertical transistor device;

removing said patterned etch mask; and

performing a second deposition process to form a second layer of top spacer material on said remaining portion of said first layer of top spacer material and on said second vertical transistor device, wherein said first top spacer comprises said remaining portion of said first layer of top spacer material and said second layer of top spacer material and said second top spacer comprises said second layer of top spacer material.

5. The method of claim 1, wherein forming said first and said second top spacer comprises:

performing a deposition process to form a layer of top spacer material for both said first and second vertical transistor devices, said layer of top spacer material having an as-deposited initial vertical thickness;

forming a patterned etch mask above said layer of top spacer material that exposes a portion of said layer of top spacer material; and

performing a timed recess etching process through said patterned etch mask to remove a portion of said as-deposited initial vertical thickness of said exposed portion of said layer of top spacer material to thereby defined a reduced-thickness portion of said layer of top spacer material, wherein said first top spacer comprises said layer of top spacer material having said as-deposited initial vertical thickness and said second top spacer comprises said reduced-thickness portion of said layer of top spacer material.

6. The method of claim 2, wherein performing said at least one epitaxial deposition process comprises:

performing a first epitaxial deposition process to form said first doped top source/drain structure, wherein said first top source/drain structure comprises one of N-type and P-type dopants; and

performing a second epitaxial deposition process to form said second doped top source/drain structure, wherein said second top source/drain structure comprises dopants that are of an opposite type to said dopants present in said first doped top source/drain structure.

7. The method of claim 1, wherein performing said anneal process comprises performing said anneal process at a temperature that falls within a range of about 800-1200°

C. for a duration of about 1-100 seconds.

8. The method of claim 1, wherein said first spacer thickness is about 1-6 nm greater than said second spacer thickness.

9. The method of claim 1, wherein at least one of said first and second vertically-oriented channel semiconductor structures is comprised of a semiconductor material that is different than a semiconductor material of said semiconductor substrate.

10. The method of claim 1, wherein performing said anneal process causes said dopants to migrate such that said first vertical transistor device has a first effective channel length and said second vertical transistor device has a second effective channel length that is less than said first effective channel length of said first vertical transistor device.

11. The method of claim 10, wherein said first effective channel length is about 1-6 nm greater than said second effective channel length.

12. The method of claim 1, wherein the first and a second vertically-oriented channel semiconductor structures have substantially the same physical size and substantially the same overall configuration when viewed from above.

13. A method comprising:

forming a first and a second vertically-oriented channel semiconductor structure for, respectively, a first and a second vertical transistor device above a semiconductor substrate;

performing a first deposition process to form a first layer of top spacer material comprising a first spacer material for both said first and second vertical transistor devices;

performing a second deposition process to form a second layer of top spacer material comprising a second spacer material on said first layer of top spacer material, wherein said second spacer material is a different material than said first spacer material;

forming a patterned etch mask above said second layer of top spacer material that exposes a portion of said second layer of top spacer material;

performing a selective etching process through said patterned etch mask to selectively remove said exposed portion of said second layer of top spacer material relative to said first layer of top spacer material so as to define;

a first top spacer with a first spacer thickness that is positioned around said first vertically-oriented channel semiconductor structure, said first top spacer comprising said first layer of top spacer material and said second layer of top spacer material; and

a second top spacer with a second spacer thickness that is positioned around said second vertically-oriented channel semiconductor, wherein said second top spacer comprises said first layer of top spacer material and wherein said first spacer thickness is greater than said second spacer thickness;

performing at least one epitaxial deposition process to form;

a first doped top source/drain structure around said first vertically-oriented channel semiconductor structure and above said first top spacer; and

a second doped top source/drain structure around said second vertically-oriented channel semiconductor structure and above said second top spacer; and

performing an anneal process so as to cause;

dopant atoms in said first doped top source/drain structure to migrate into said first vertically-oriented channel semiconductor structure; and

dopant atoms in said second doped top source/drain structure to migrate into said second vertically-oriented channel semiconductor structure.

14. The method of claim 13, wherein said first spacer thickness is about 1-6 nm greater than said second spacer thickness and wherein performing said anneal process causes said dopants to migrate such that first vertical transistor device has a first effective channel length and the second vertical transistor device has a second effective channel length, wherein the first effective channel length is about 1-6 nm greater than said second effective channel length.

15. The method of claim 13, wherein final first and second gate structures for, respectively, said first and second vertical transistor devices are formed prior to the formation of said first layer of top spacer material.

16. The method of claim 13, wherein performing said anneal process causes said dopants to migrate such that said first vertical transistor device has a first effective channel length and said second vertical transistor device has a second effective channel length that is less than said first effective channel length of said first vertical transistor device.

17. A method comprising:

forming a first and a second vertically-oriented channel semiconductor structure for, respectively, a first and a second vertical transistor device above a semiconductor substrate;

forming a first and a second top spacer, respectively, around said first and second vertically-oriented channel semiconductor structures, said first and second top spacers having, respectively, a first and a second spacer thickness, wherein said first spacer thickness is about 1-6 nm greater than said second spacer thickness;

performing at least one epitaxial deposition process to form;

a first doped top source/drain structure around said first vertically-oriented channel semiconductor structure and above said first top spacer; and

a second doped top source/drain structure around said second vertically-oriented channel semiconductor structure and above said second top spacer; and

performing an anneal process so as to cause;

dopant atoms in said first doped top source/drain structure to migrate into said first vertically-oriented channel semiconductor structure such that said first vertical transistor device has a first effective channel length; and

dopant atoms in said second doped top source/drain structure to migrate into said second vertically-oriented channel semiconductor structure such that said second vertical transistor device has a second effective channel length that is about 1-6 nm less than said first effective channel length.

18. The method of claim 17, wherein forming said first and said second top spacer comprises:

performing a first deposition process to form a first layer of top spacer material comprising a first spacer material for both said first and second vertical transistor devices;

performing a second deposition process to form a second layer of top spacer material comprising a second spacer material on said first layer of top spacer material, wherein said second spacer material is a different material than said first spacer material;

forming a patterned etch mask above said second layer of top spacer material that exposes a portion of said second layer of top spacer material; and

performing a selective etching process through said patterned etch mask to selectively remove said exposed portion of said second layer of top spacer material relative to said first layer of top spacer material, wherein said first top spacer comprises said first layer of top spacer material and said second layer of top spacer material and said second top spacer comprises said first layer of top spacer material.

19. The method of claim 17, wherein forming said first and said second top spacer comprises:

performing a first deposition process to form a first layer of top spacer material for both said first and second vertical transistor devices;

forming a patterned etch mask above said first layer of top spacer material that exposes a portion of said first layer of top spacer material for said second vertical transistor device;

performing an etching process through said patterned etch mask to selectively remove said exposed portion of said first layer of top spacer material for said second vertical transistor device and thereby leave a remaining portion of said first layer of top spacer material for said first vertical transistor device;

removing said patterned etch mask; and

performing a second deposition process to form a second layer of top spacer material on said remaining portion of said first layer of top spacer material and on said second vertical transistor device, wherein said first top spacer comprises said remaining portion of said first layer of top spacer material and said second layer of top spacer material and said second top spacer comprises said second layer of top spacer material.

20. The method of claim 17, wherein forming said first and said second top spacer comprises:

performing a deposition process to form a layer of top spacer material for both said first and second vertical transistor devices, said layer of top spacer material having an as-deposited initial vertical thickness;

forming a patterned etch mask above said layer of top spacer material that exposes a portion of said layer of top spacer material; and

performing a timed recess etching process through said patterned etch mask to remove a portion of said as-deposited initial vertical thickness of said exposed portion of said layer of top spacer material to thereby defined a reduced-thickness portion of said layer of top spacer material, wherein said first top spacer comprises said layer of top spacer material having said as-deposited initial vertical thickness and said second top spacer comprises said reduced-thickness portion of said layer of top spacer material.