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Methods of forming vertical transistor devices with different effective gate lengths

  • US 9,935,018 B1
  • Filed: 02/17/2017
  • Issued: 04/03/2018
  • Est. Priority Date: 02/17/2017
  • Status: Active Grant
First Claim
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1. A method comprising:

  • forming a first and a second vertically-oriented channel semiconductor structure for, respectively, a first and a second vertical transistor device above a semiconductor substrate;

    forming a first and a second top spacer, respectively, around said first and second vertically-oriented channel semiconductor structures, said first and second top spacers having, respectively, a first and a second spacer thickness, wherein said first spacer thickness is greater than said second spacer thickness;

    performing at least one epitaxial deposition process to form;

    a first doped top source/drain structure around said first vertically-oriented channel semiconductor structure and above said first top spacer; and

    a second doped top source/drain structure around said second vertically-oriented channel semiconductor structure and above said second top spacer; and

    performing an anneal process so as to cause;

    dopant atoms in said first doped top source/drain structure to migrate into said first vertically-oriented channel semiconductor structure; and

    dopant atoms in said second doped top source/drain structure to migrate into said second vertically-oriented channel semiconductor structure.

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