Method for forming semiconductor structure

• US 9,935,024 B2
• Filed: 10/07/2016
• Issued: 04/03/2018
• Est. Priority Date: 04/28/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Pei-Chun, Chang, Wei-Sen, Kuo, Tin-Hao, Tsai, Hao-Yi
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/288,041
• Publication Number:
  US 20170316989A1
• Time in Patent Office: 543 Days
• Field of Search: 32475019, 32475403, 32475501, 257 48, 257737, 257762, 257774, 257780, 257E21502, 257E21504, 257E21506, 257E21531, 257E21577, 257E23008, 257E2301, 257E2302, 257E23023, 257E23068, 361760, 438 17, 438106, 438108, 438613
• CPC Class Codes: G01R 1/073 Multiple probes
• CPC Class Codes: G01R 31/00 Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere measuring superconductive properties G01R33/1238; testing or measuring semiconductors or solid state devices during manufacture H01L22/00; testing line transmission systems H04B3/46
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03831 involving a chemical process, e.g. etching the bonding area
• CPC Class Codes: H01L 2224/03845 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/03921 by repairing the bonding area damaged by the probing step
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 : Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05008 : Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 : the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 : the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13026 : relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed over the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad, and the protection layer has a trench. The semiconductor device structure includes a conductive structure formed in the trench and on the protection layer. The conductive structure is electrically connected to the conductive pad, and the conductive structure has a concave top surface, and the lowest point of the concave top surface is higher than the top surface of the protection layer.

Claims

1. A method for forming the semiconductor device structure, comprising:

forming a plurality of dies over a first substrate of a first wafer;

forming a conductive structure over one of the dies, wherein the conductive structure defines a curved top surface;

forming a solder material on the conductive structure;

performing a functional test on the conductive structure through the solder material; and

removing the solder material by an etching process, such that the curved top surface of the conductive structure remains on the conductive structure after the etching process.

2. The method for forming the semiconductor device structure as claimed in claim 1, wherein the step of removing the solder material is performed without using a chemical polishing (CMP) process.

3. The method for forming the semiconductor device structure as claimed in claim 1, further comprising:

forming a seed layer over the conductive structure, wherein the seed layer has a curved top surface; and

forming a post-passivation interconnect (PPI) structure over the seed layer, wherein the PPI structure is electrically connected to the conductive structure by the seed layer.

4. The method for forming the semiconductor device structure as claimed in claim 3, further comprising:

forming an under bump metallurgy (UBM) layer over the PPI structure; and

forming an electrical connector formed over the UBM layer, wherein the electrical connector is electrically connected to the PPI structure by the UBM layer.

5. The method for forming the semiconductor device structure as claimed in claim 1, further comprising:

dicing the first wafer to obtain the plurality of dies;

putting one of the dies over a second substrate of a second wafer; and

forming a conductive pillar structure over the second substrate, wherein the dies are surrounded by the conductive pillar structure.

6. The method for forming the semiconductor device structure as claimed in claim 5, further comprising:

forming a package layer adjacent to the dies after forming the conductive pillar structure, wherein the dies are insulated from the conductive pillar structure by the package layer.

7. The method for forming the semiconductor device structure as claimed in claim 1, wherein the conductive structure is formed in a protective layer, the protective layer has a top surface, an apex of the curved top surface of the conductive structure remains above the top surface of the protective layer.

8. A method for forming the semiconductor device structure, comprising:

forming a conductive pad over a substrate;

forming a protection layer over the conductive pad, wherein the protection layer has a trench;

forming a conductive structure in the trench and on the protection layer, wherein the conductive structure defines a curved top surface, and the conductive structure is electrically connected to the conductive pad;

forming a solder material on the conductive structure; and

removing the solder material by an etching process, such that the curved top surface of the conductive structure remains on the conductive structure after the etching process.

9. The method for forming the semiconductor device structure as claimed in claim 8, wherein the step of removing the solder material is performed without using a chemical polishing (CMP) process.

10. The method for forming the semiconductor device structure as claimed in claim 8, further comprising:

forming a seed layer over the conductive structure, wherein the seed layer has a curved top surface and a curved bottom surface.

11. The method for forming the semiconductor device structure as claimed in claim 10, further comprising:

forming a post-passivation interconnect (PPI) structure over the seed layer, wherein the PPI structure is electrically connected to the conductive structure by the seed layer, and the PPI structure has a curved bottom surface.

12. The method for forming the semiconductor device structure as claimed in claim 11, wherein the curved bottom surface of the PPI structure is in direct contact with the curved top surface of the seed layer.

13. The method for forming the semiconductor device structure as claimed in claim 8, further comprising:

forming a conductive pillar structure adjacent to the conductive structure, wherein the conductive structure is surrounded by the conductive pillar structure.

14. The method for forming the semiconductor device structure as claimed in claim 8, further comprising:

forming a package layer adjacent to the conductive pillar structure, wherein the conductive structure is insulated from the conductive pillar structure by the package layer.

15. The method for forming the semiconductor device structure as claimed in claim 8, wherein the conductive structure has a curved top surface that defines an apex, and an apex of the curved top surface is higher than a top surface of the protection layer.

16. A method for forming the semiconductor device structure, comprising:

forming a protection layer over a first substrate, wherein the protection layer has a trench;

forming a conductive structure in the trench and on the protection layer, wherein the conductive structure defines a curved top surface;

forming a solder material on the conductive structure;

removing the solder material by an etching process, such that the curved top surface of the conductive structure remains on the conductive structure after the etching process; and

forming a seed layer over the conductive structure, wherein the seed layer has a curved bottom surface in direct contact with the curved top surface of the conductive structure.

17. The method for forming the semiconductor device structure as claimed in claim 16, wherein the step of removing the solder material is performed without using a chemical polishing (CMP) process.

18. The method for forming the semiconductor device structure as claimed in claim 16, further comprising:

forming a post-passivation interconnect (PPI) structure formed over the seed layer, wherein the PPI structure is electrically connected to the conductive structure by the seed layer, and the PPI structure has a curved bottom surface.

19. The method for forming the semiconductor device structure as claimed in claim 16, further comprising:

forming a conductive pillar structure adjacent to the conductive structure, wherein the conductive pillar structure is surrounded by the conductive pillar structure.

20. The method for forming the semiconductor device structure as claimed in claim 19, further comprising:

forming a package layer adjacent to the conductive pillar structure, wherein the conductive structure is insulated from the conductive pillar structure by the package layer.