Hybrid interconnect for chip stacking

• US 9,935,081 B2
• Filed: 08/20/2014
• Issued: 04/03/2018
• Est. Priority Date: 08/20/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Pan, Kuo Lung, Chen, Yu-Feng, Chen, Chen-Shien, Lii, Mirng-Ji
• Primary Examiner(s): PARENDO, KEVIN A
• Application Number:
  US14/464,509
• Publication Number:
  US 20160056125A1
• Time in Patent Office: 1,322 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/141 Disposition
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/171 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/81986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/82105 : by using a preform
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92133 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/92242 : the first connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias

Abstract

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels.

Claims

1. A semiconductor package comprising:

first contact pads over a first side of a substrate;

second contact pads over the first side of the substrate, wherein the first contact pads and the second contact pads physically contact a same planar surface of the substrate;

a first semiconductor device covering the second contact pads, wherein the first semiconductor device has a functional circuit comprising an active device, wherein the first semiconductor device comprises third contact pads on a first side of the first semiconductor device facing away from the substrate, wherein a second side of the first semiconductor device opposing the first side of the first semiconductor device is attached to the first side of the substrate, wherein the first contact pads are laterally removed from the first semiconductor device;

a plurality of conductive channels extending through the first semiconductor device, wherein the conductive channels are electrically connected to the second contact pads;

a second semiconductor device over the first semiconductor device and having first conductive pillars and second conductive pillars, wherein a first portion of the second semiconductor device is electrically connected to the third contact pads via the first conductive pillars, and a second portion of the second semiconductor device is electrically connected to the first contact pads via the second conductive pillars, wherein a width of the second conductive pillars is larger than a width of the first conductive pillars; and

a third semiconductor device over the first semiconductor device, wherein a first portion of the third semiconductor device is electrically connected to the third contact pads, and a second portion of the third semiconductor device is electrically connected to the conductive channels.

2. The semiconductor package of claim 1, wherein the first contact pads and the second contact pads comprise different sizes.

3. The semiconductor package of claim 1, wherein the first conductive pillars and the second conductive pillars of the second semiconductor device comprise copper.

4. The semiconductor package of claim 1, wherein the first semiconductor device comprises metallization layers that electrically connect the second semiconductor device and the third semiconductor device.

5. The semiconductor package of claim 1, wherein the first semiconductor device is partially recessed in the substrate.

6. The semiconductor package of claim 1, wherein a height of the second conductive pillars is larger than a height of the first conductive pillars.

7. The semiconductor package of claim 6, wherein the second conductive pillars are coupled to power signals or ground signals.

8. The semiconductor package of claim 1, wherein each of the plurality of conductive channels has a first width at a first interface between the plurality of conductive channels and the first side of the first semiconductor device, and wherein each of the plurality of conductive channels has a second width at a second interface between the plurality of conductive channels and the second contact pads, the first width being larger than the second width.

9. The semiconductor package of claim 8, wherein a width of each of the conductive channels decreases continuously from the first interface to the second interface.

10. The semiconductor package of claim 1, wherein the second side of the first semiconductor device is attached to the first side of the substrate via an adhesive layer, wherein the adhesive layer fills a gap between the substrate and the first semiconductor device.

11. The semiconductor package of claim 10, further comprising an underfill between the substrate and the second semiconductor device, and between the substrate and the third semiconductor device, wherein a first sidewall of the adhesive layer is covered by the underfill, and a second sidewall of the adhesive layer opposing the first sidewall is free of the underfill.

12. A semiconductor package comprising:

first contact pads over a first side of a substrate;

second contact pads over the first side of the substrate, wherein the first contact pads and the second contact pads physically contact a same planar surface of the substrate;

a first semiconductor device covering the second contact pads, wherein the first semiconductor device has a functional circuit comprising an active device, wherein the first semiconductor device comprises third contact pads on a first side of the first semiconductor device facing away from the substrate, wherein a second side of the first semiconductor device opposing the first side of the first semiconductor device is attached to the first side of the substrate, wherein the first contact pads are laterally removed from the first semiconductor device;

a plurality of conductive channels extending through the first semiconductor device, wherein the conductive channels are electrically connected to the second contact pads, wherein a width of the conductive channels, measured along a first direction parallel to the first side of the first semiconductor device, decreases along a second direction from the first side of the first semiconductor device to the second side of the first semiconductor device;

a second semiconductor device over the first semiconductor device and having first conductive pillars and second conductive pillars, wherein a first portion of the second semiconductor device is electrically connected to the third contact pads via the first conductive pillars, and a second portion of the second semiconductor device is electrically connected to the first contact pads via the second conductive pillars, wherein a width of the second conductive pillars is larger than a width of the first conductive pillars, wherein there is no conductive channel between the substrate and the first conductive pillars of the second semiconductor device; and

a third semiconductor device over the first semiconductor device, wherein a first portion of the third semiconductor device is electrically connected to the third contact pads, and a second portion of the third semiconductor device is electrically connected to the conductive channels.

13. The semiconductor package of claim 12, wherein each of the conductive channels fills an opening in the first semiconductor device, wherein the opening has a trapezoidal cross-section.

14. The semiconductor package of claim 12, wherein a height of the second conductive pillars is larger than a height of the first conductive pillars.

15. The semiconductor package of claim 12, wherein the second contact pads are at least partially recessed below a surface of the substrate.

16. The semiconductor package of claim 15, wherein the second contact pads are disposed in a first recess of the substrate, and wherein the first semiconductor device is disposed in the first recess of the substrate.

17. A semiconductor package comprising:

first contact pads over a first side of a substrate;

second contact pads over the first side of the substrate, wherein the first contact pads and the second contact pads physically contact a same planar surface of the substrate;

a first semiconductor device covering the second contact pads, wherein the first semiconductor device has a functional circuit comprising an active device, wherein the first semiconductor device comprises third contact pads on a first side of the first semiconductor device facing away from the substrate, wherein a second side of the first semiconductor device opposing the first side of the first semiconductor device is attached to the first side of the substrate, wherein the first contact pads are laterally removed from the first semiconductor device;

a plurality of conductive channels extending through the first semiconductor device, wherein the conductive channels are electrically connected to the second contact pads and extend above the first side of the first semiconductor device, wherein there is no conductive channel between the substrate and the third contact pads of the first semiconductor device;

a second semiconductor device over the first semiconductor device and having first conductive pillars and second conductive pillars, wherein a first portion of the second semiconductor device is electrically connected to the third contact pads via the first conductive pillars, and a second portion of the second semiconductor device is electrically connected to the first contact pads via the second conductive pillars, wherein a width of the second conductive pillars is larger than a width of the first conductive pillars; and

a third semiconductor device over the first semiconductor device, wherein a first portion of the third semiconductor device is electrically connected to the third contact pads, and a second portion of the third semiconductor device is electrically connected to the conductive channels.

18. The semiconductor package of claim 17, wherein a first portion of the conductive channels extends from the second contact pads to the first side of the first semiconductor device, and a second portion of the conductive channels extends above the first side of the first semiconductor device toward the third semiconductor device, wherein a width of the first portion of the conductive channels increases continuously along a direction from the second side of the first semiconductor device to the first side of the first semiconductor device.

19. The semiconductor package of claim 18, wherein the second conductive pillars are connected to power signals or ground signals.

20. The semiconductor package of claim 17, wherein a first distance between the first side of the first semiconductor device and a surface of the second semiconductor device facing the substrate is the same as a second distance between the first side of the first semiconductor device and a surface of the third semiconductor device facing the substrate.