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Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications

  • US 9,935,088 B2
  • Filed: 03/13/2017
  • Issued: 04/03/2018
  • Est. Priority Date: 08/13/2015
  • Status: Active Grant
First Claim
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1. A package structure, comprising:

  • a photonics package comprising;

    a first integrated circuit chip comprising active circuitry, an insulating layer, an active silicon layer disposed adjacent to the insulating layer, and a BEOL (back-end-of-line) structure formed over the active silicon layer;

    an integrated optical waveguide structure patterned from the active silicon layer of the first integrated circuit chip;

    an optoelectronics device mounted on the insulating layer of the first integrated circuit chip in alignment with at least a portion of the integrated optical waveguide structure, wherein the optoelectronics device is coupled to the active circuitry of the first integrated circuit chip; and

    an interposer bonded to the BEOL structure of the first integrated circuit chip, the interposer comprising at least one substrate having a plurality of conductive through vias and wiring to provide electrical connections to the BEOL structure;

    a second integrated circuit chip coupled to the photonics package by flip-chip bonding the interposer of the photonics package to an active surface of the second integrated circuit chip, wherein the second integrated circuit chip comprises a processor coupled to the active circuitry of the first integrated circuit chip;

    a package interposer comprising a first side and a second side opposite the first side, wherein the second integrated circuit is mounted to the first side of the package interposer with the photonics package disposed within a hole formed through the package interposer from the first side of the package interposer to the second side of the package interposer; and

    an application board, wherein the second side of the package interposer is mounted to the application board.

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