Non-volatile memory and method for programming and reading a memory array having the same

• US 9,935,113 B2
• Filed: 05/25/2017
• Issued: 04/03/2018
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Wu, Meng-Yi, Chen, Hsin-Ming
• Primary Examiner(s): Norman, James G
• Application Number:
  US15/604,672
• Publication Number:
  US 20170345828A1
• Time in Patent Office: 313 Days
• Field of Search: None
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 : Silicon carbide
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42376 : characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate
• CPC Class Codes: H02M 3/07 : using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/075 : including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 2005/00195 : using FET's
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/134 : with field-effect transistors
• CPC Class Codes: H03K 5/159 : Applications of delay lines not covered by the preceding subgroups
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

Claims

1. A non-volatile memory, comprising:

a fin structure;

a first fin field effect transistor (FinFET), formed on the fin structure and having a first gate, a first source region, and a first drain region;

a second FinFET, formed on the fin structure and having a second gate, a second drain region, and a second source region coupled to the first drain region;

an antifuse structure, formed on the fin structure and having a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region, wherein the SDB isolation structure is formed between the first source/drain region and the second source/drain region, a top surface of the SDB isolation structure is covered by the sharing gate, and the first source/drain region is coupled to the second drain region;

a third FinFET, formed on the fin structure and having a third gate, a third source region, and a third drain region coupled to the second source/drain region; and

a fourth FinFET, formed on the fin structure and having a fourth gate, a fourth source region, and a fourth drain region coupled to the third source region.

2. The non-volatile memory of claim 1, wherein the antifuse structure forms a first antifuse element and a second antifuse element.

3. The non-volatile memory of claim 2, wherein the first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell.

4. The non-volatile memory of claim 1, wherein the SDB isolation structure isolates the first source/drain region and the second source/drain region.

5. The non-volatile memory of claim 1, wherein the first FinFET further comprises:

a first source/drain extension area, coupled to the first source region and partially covered by the first gate; and

a second source/drain extension area, coupled to the first drain region and partially covered by the first gate;

the antifuse structure further comprises;

a fifth source/drain extension area, coupled to the first source/drain region and partially covered by the sharing gate; and

a sixth source/drain extension area, coupled to the second source/drain region and partially covered by the sharing gate; and

the fourth FinFET further comprises;

a ninth source/drain extension area, coupled to the fourth drain region and partially covered by the fourth gate; and

a tenth source/drain extension area, coupled to the fourth source region and partially covered by the fourth gate.

6. The non-volatile memory of claim 5, wherein the second FinFET further comprises:

a third source/drain extension area, coupled to the second source region and partially covered by the second gate; and

a fourth source/drain extension area, coupled to the second drain region and partially covered by the second gate; and

wherein the third FinFET further comprises;

a seventh source/drain extension area, coupled to the third drain region and partially covered by the third gate; and

an eighth source/drain extension area, coupled to the third source region and partially covered by the third gate.

7. The non-volatile memory of claim 1, wherein the second gate is coupled to the third gate.

8. The non-volatile memory of claim 1, wherein the first source region is coupled to the fourth source region.

9. The non-volatile memory of claim 1, wherein the first gate is coupled to the fourth gate.

10. The non-volatile memory of claim 1, wherein the fin structure is a P well over a silicon substrate, and all source regions, all drain regions and all source/drain regions are formed by an epitaxial silicon phosphorous (SiP) or silicon carbide (SiC) process.

11. The non-volatile memory of claim 1, wherein the SDB isolation structure is formed of silicon oxide.

12. The non-volatile memory of claim 1, wherein each of the first gate, the second gate, the third gate and the fourth gate has a U shape to overlap three lateral sides of the fin structure.

13. The non-volatile memory of claim 1, wherein the sharing gate has a U shape to overlap three lateral sides of the SDB isolation structure.

14. The non-volatile memory of claim 1, wherein each of the first gate, the second gate, the third gate, the fourth gate and the sharing gate has a metal layer and a gate oxide layer formed between the metal layer and the fin structure.

15. The non-volatile memory of claim 14, wherein thicknesses of the metal layers of the first gate, the second gate, the third gate, the fourth gate and the sharing gate are the same, and thicknesses of the gate oxide layers of the first gate, the second gate, the third gate, the fourth gate and the sharing gate are the same.

16. The non-volatile memory of claim 1, wherein the sharing gate is a poly over diffusion edge (PODE) of the non-volatile memory.

17. A method for programming a memory array, comprising:

providing a memory array comprising a plurality of non-volatile memories each being the non-volatile memory type of claim 1;

providing a first voltage ranging from 0.6 volts to 1.4 volts to the first gates or the fourth gates of the non-volatile memories at a selected row of the memory array;

providing a second voltage ranging from 1.2 volts to 2.2 volts to the second gates and the third gates of the plurality of the non-volatile memories of the memory array;

providing a third voltage ranging from 3.6 volts to 5.5 volts to the sharing gates of the plurality of the non-volatile memories of the memory array; and

providing a ground voltage to the first source regions of the non-volatile memories at a selected column of the memory array;

wherein the third voltage is greater than the first and the second voltages, and the first and second voltages are greater than the ground voltage.

18. The method of claim 17, further comprising:

providing the first voltage to the first source regions of the non-volatile memories at unselected columns of the memory array.

19. The method of claim 17, further comprising:

providing the ground voltage to the first gates and the fourth gates of the non-volatile memories at unselected rows of the memory array.