MOSFET termination trench

• US 9,935,193 B2
• Filed: 03/20/2015
• Issued: 04/03/2018
• Est. Priority Date: 02/09/2012
• Status: Active Grant

• Current Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Inventors: Azam, Misbah Ul, Terrill, Kyle
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): REIDA, MOLLY KAY
• Application Number:
  US14/663,872
• Publication Number:
  US 20150194495A1
• Time in Patent Office: 1,110 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon can be deposited into the termination trench. A second oxide can be deposited above the first polysilicon. A mask can be deposited above the second oxide and the termination trench. The first oxide can be removed from the core trench. A third oxide can be deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench.

Claims

1. A method comprising:

forming a core trench and a termination trench in a substrate, said termination trench is wider than said core trench;

depositing a first dielectric into said core trench and that lines the sidewalls and bottom of said termination trench;

depositing a first conductive material into said termination trench;

depositing a second dielectric above said first conductive material;

removing said first dielectric from said core trench;

depositing a third dielectric that lines the sidewalls and bottom of said core trench, said first dielectric within said termination trench is thicker than said third dielectric within said core trench; and

depositing a second conductive material into said core trench, said second conductive material is deeper than said first conductive material.

2. The method of claim 1, wherein said termination trench is deeper than said core trench.

3. The method of claim 1, further comprising:

implanting a doped region into a mesa of said substrate located between said core trench and said termination trench.

4. The method of claim 3, wherein said mesa is formed by said core trench and said termination trench.

5. The method of claim 1, wherein said first conductive material is wider than said second conductive material.

6. The method of claim 1, further comprising:

depositing a fourth dielectric above said first and second conductive material.

7. The method of claim 6, wherein said fourth dielectric further contacts said first and second conductive materials.

8. The method of claim 1, further comprising:

removing a portion of said first conductive material and a portion of said first dielectric to form a substantially planarized surface.

9. A method comprising:

forming a core trench and a termination trench in a substrate, said terminatioon trench is wider than said core trench;

depositing a first oxide into said core trench and that lines the sidewalls and bottom of said termination trench;

depositing a first polysilicon into said termination trench;

depositing a second oxide above said first polysilicon;

removing said first oxide from said core trench;

deposifing a third oxide that lines the sidewalls and bottom of said core trench, said first oxide within said termination trench is thicker than said third oxide within said core trench; and

depositing a second polysilicon into said core trench, said second polysilicon is deeper than said first polysilicon.

10. The method of claim 9, further comprising:

depositing a mask above said second oxide and said termination trench.

11. The method of claim 9, wherein said first oxide fills said core trench.

12. The method of claim 9, wherein said termination trench is deeper than said core trench.

13. The method of claim 9, further comprising:

implanting a doped region into a mesa of said substrate located between said core trench and said termination trench.

14. The method of claim 13, wherein said mesa is formed by said core trench and said termination trench.

15. The method of claim 9, further comprising:

depositing a fourth dielectric above said first and second polysilicon.

16. A method comprising:

forming a core trench and a termination trench in a substrate, said termination trench is wider than said core trench;

depositing a first oxide layer that fills said core trench and lines the sidewalls is and bottom of said termination trench;

depositing a first polysilicon into said termination trench;

depositing a second oxide layer above said first polysilicon;

depositing a mask above said second oxide layer and said termination trench,

removing said first oxide layer from said core trench;

depositing a third oxide layer that lines the sidewalls and bottom of said core trench, said first oxide layer within said termination trench is thicker than said third oxide layer within said core trench, and

depositing a second polysilicon into said core trench, said second polysilicon is deeper than said first polysilicon.

17. The method of claim 16, wherein said termination trench is deeper than said core trench.

18. The method of claim 16, further comprising:

before said depositing a mask, performing an oxide polishing process to planarize said second oxide layer.

19. The method of claim 16, further comprising:

implanting a doped region into a mesa of said substrate located between said core trench and said termination trench.

20. The method of claim 16, further comprising:

depositing a fourth dielectric above said first and second polysilicon.