Radio communication apparatus, and radio communication method

• US 9,935,673 B2
• Filed: 07/18/2017
• Issued: 04/03/2018
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Miyoshi, Kenichi, Suzuki, Hidetoshi, Hiramatsu, Katsuhiko, Wengerter, Christian, Golitschek Edler Von Elbwart, Alexander
• Primary Examiner(s): Timory, Kabir A
• Application Number:
  US15/652,731
• Publication Number:
  US 20170317708A1
• Time in Patent Office: 259 Days
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 15/00 Suppression or limitation of noise or interference by means associated with receiver H04B1/10
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 25/0202 Channel estimation
• CPC Class Codes: H04L 25/0212 of impulse response
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/183 Multiresolution systems
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 5/0046 Determination of how many bits are transmitted on different sub-channels

Abstract

Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated.

Claims

1. A radio communication apparatus comprising:

a receiver, which, in operation, receives control information associated with a number of bits; and

circuitry, which, in operation;

generates a bit sequence by forcibly setting each place of the number of bits determined from the control information out of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

modulates the bit sequence by mapping the plurality of bits on a single modulation mapper, the single modulation mapper having first signal points,

wherein said circuitry, in operation, forcibly sets each place of the number of bits to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, a distance between the second signal points being equivalent to a largest of distance existing among the first signal points in an I-Q plane of the single modulation mapper.

2. The radio communication apparatus according to claim 1, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BP K, QPSK or 8-PSK which is included in the single modulation mapper.

3. The radio communication apparatus according to claim 1, wherein the control information is associated with two as the number of bits, and said circuitry, in operation, generates the bit sequence by forcibly setting each place of the lower two bits of the plurality of bits to the 1.

4. The radio communication apparatus according to claim 1, wherein the control information is associated with three as the number of bits, and said circuitry, in operation, generates the bit sequence by forcibly setting each place of the lower three bits of the plurality of bits to the 1.

5. The radio communication apparatus according to claim 1, wherein the control information is associated with four as the number of bits, and said circuitry, in operation, generates the bit sequence by forcibly setting each place of the lower four bits of the plurality of bits to the 1.

6. A radio communication apparatus comprising:

a receiver, which, in operation, receives control information associated with a number of bits; and

circuitry, which, in operation;

generates a bit sequence by forcing setting each place of the number of bits determined from the control information out of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

modulates the bit sequence by mapping the plurality of bits on a single modulation mapper, the single modulation mapper having first signal points,

wherein said circuitry, in operation, forcibly sets each place of the number of bits to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, such that said modulation symbol is detected by positive or negative decision only with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.

7. The radio communication apparatus according to claim 6, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

8. The radio communication apparatus according to claim 6, wherein the control information is associated with two as the number of bits, and said circuitry, in operation, generates the bit sequence by forcibly setting each place of the lower two bits of the plurality of bits to the 1.

9. The radio communication apparatus according to claim 6, wherein the control information is associated with three as the number of bits, and said circuitry, in operation, generates the bit sequence by forcibly setting each place of the lower three bits of the plurality of bits to the 1.

10. The radio communication apparatus according to claim 6, wherein the control information is associated with four as the number of bits, and said circuitry, in operation, generates the bit sequence by forcibly setting each place of the lower four bits of the plurality of bits to the 1.

11. A radio communication method comprising:

receiving control information associated with a number of bits;

generating a bit sequence by forcibly setting each place of the number of bits determined from the control information out of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

modulating the bit sequence by mapping the plurality of bits on a single modulation mapper, the single modulation mapper having first signal points,

wherein each place of the number of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, a distance between the second signal points being equivalent to a largest of distances existing among the first signal points in an I-Q plane of the single modulation mapper.

12. The radio communication method according to claim 11, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

13. The radio communication method according to claim 11, wherein the control information is associated with two as the number of bits, and the bit sequence is generated by forcibly setting each place of the lower two bits of the plurality of bits to the 1.

14. The radio communication method according to claim 11, wherein the control information is associated with three as the number of bits, and the bit sequence is generated by forcibly setting each place of the lower three bits of the plurality of bits to the 1.

15. The radio communication method according to claim 11, wherein the control information is associated with four as the number of bits, and the bit sequence is generated by forcibly setting each place of the lower four bits of the plurality of bits to the 1.

16. A radio communication method comprising:

receiving control information associated with a number of bits;

generating a bit sequence by forcibly setting each place of the number of bits determined from the control information out of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and

modulating the bit sequence by mapping the plurality of bits on a single modulation mapper, the single modulation mapper having first signal points,

wherein each place of the number of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, such that said modulation symbol is detected by positive or negative decision only with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.

17. The radio communication method according to claim 16, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

18. The radio communication method according to claim 16, wherein the control information is associated with two as the number of bits, and the bit sequence is generated by forcibly setting each place of the lower two bits of the plurality of bits to the 1.

19. The radio communication method according to claim 16, wherein the control information is associated with three as the number of bits, and the bit sequence is generated by forcibly setting each place of the lower three bits of the plurality of bits to the 1.

20. The radio communication method according to claim 16, wherein the control information is associated with four as the number of bits, and the bit sequence is generated by forcibly setting each place of the lower four bits of the plurality of bits to the 1.