Method and apparatus for model identification and predistortion

• US 9,935,810 B1
• Filed: 03/07/2017
• Issued: 04/03/2018
• Est. Priority Date: 03/07/2017
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Hammler, Nikolaus H., Dick, Christopher H.
• Primary Examiner(s): Perez, James M
• Application Number:
  US15/451,933
• Time in Patent Office: 392 Days
• Field of Search: 375295-297, 375354-355
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3258 based on polynomial terms
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 27/368 adaptive predistortion

Abstract

A model identification system includes an analog to digital converter (ADC). The ADC includes a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate. The ADC further includes a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the second digital signal and a first sampling matrix. The first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is a row vector including a plurality of elements.

Claims

1. A model identification system, comprising:

an analog to digital converter (ADC) including;

a conversion circuit configured to receive a first analog signal and generate a first digital signal including samples having a first rate by sampling the first analog signal at the first rate; and

a first digital signal processing (DSP) circuit configured to generate a second digital signal including samples having a second rate less than the first rate based on the first digital signal and a first sampling matrix,

wherein the first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is being a row vector including a plurality of elements.

2. The model identification system of claim 1, further comprising:

a first system configured to generate the first analog signal based on a second analog signal, and provide the first analog signal to the ADC, wherein the second analog signal is generated based on a third digital signal; and

a second DSP circuit coupled to the ADC and including;

a model identification unit configured to receive the second digital signal and the third digital signal, and determine coefficients for a model of the first system based on the second digital signal, the third digital signal, and a second sampling matrix that matches the first sampling matrix.

3. The model identification system of claim 2, wherein the first DSP circuit and the second DSP circuit are synchronized.

4. The model identification system of claim 2, wherein the model identification unit is configured to determine the coefficients of the model of the first system using least squares (LS).

5. The model identification system of claim 2, wherein the second DSP circuit includes:

a predistortion unit configured to receive a fourth digital signal and generate the third digital signal by predistorting the fourth digital signal based on the coefficients for the model of the first system.

6. The model identification system of claim 5, wherein the first system is a non-linear power amplifier.

7. The model identification system of claim 2, wherein the first sampling matrix is a diagonal block random sign matrix, and

wherein the first DSP circuit includes:

a first random number generator configured to provide a first sequence of random signs for the first sampling matrix.

8. The model identification system of claim 7, wherein the first random number generator includes a first linear-feedback shift register configured to generate the first sequence of random signs.

9. The model identification system of claim 7, wherein the model identification unit includes:

a second random number generator configured to provide a second sequence of random signs for the second sampling matrix, wherein the second sequence of random signs match the first sequence of random signs.

10. The model identification system of claim 1, wherein the first DSP circuit is configured to generate a first sample of the second digital signal based on a plurality of consecutive samples of the first digital signal, and

wherein a first size of the plurality of consecutive samples equals a second size of the elements of the row vector.

11. A method, comprising:

receiving, by an analog to digital converter (ADC), a first analog signal;

generating, by a conversion circuit of the ADC, a first digital signal including samples having a first rate by sampling the first analog signal at the first rate; and

generating, by a first digital signal processing (DSP) circuit of the ADC, a second digital signal including samples having a second rate less than the first rate based on the first digital signal and a first sampling matrix,

wherein the first sampling matrix is a block diagonal matrix including a plurality of diagonal blocks, each diagonal block is being a row vector including a plurality of elements.

12. The method of claim 11, further comprising:

generating, by a first system, the first analog signal based on a second analog signal, and provide the first analog signal to the ADC, wherein the second analog signal is generated based on a third digital signal;

receiving, by a model identification unit of a second DSP circuit, the second digital signal from the ADC and the third digital signal; and

determining, by a model identification unit, coefficients for a model of the first system based on the second digital signal, the third digital signal, and a second sampling matrix that matches the first sampling matrix.

13. The method of claim 12, further comprising:

synchronizing the first DSP circuit and the second DSP circuit.

14. The method of claim 12, further comprising:

determining the coefficients of the model of the first system using least squares (LS).

15. The method of claim 12, further comprising:

receiving a fourth digital signal; and

generating the third digital signal by predistorting the fourth digital signal based on the coefficients of the model of the first system.

16. The method of claim 15, further comprising:

providing a non-linear power amplifier as the first system.

17. The method of claim 12, wherein the first sampling matrix is a diagonal block random sign matrix, further comprising:

providing, by a first random number generator, a first sequence of random signs for the first sampling matrix.

18. The method of claim 17, further comprising:

providing, by a first linear-feedback shift register, the first sequence of random signs.

19. The method of claim 17, further comprising:

generating, by a second random number generator, a second sequence of random signs matching the first sequence of random signs; and

generating the second sampling matrix using the first sequence of random signs.

20. The method of claim 11, further comprising:

generating a first sample of the second digital signal based on a plurality of consecutive samples of the first digital signal, wherein a first size of the plurality of consecutive samples equals a second size of the elements of the row vector of the first sampling matrix.