Imager array interfaces

• US 9,936,148 B2
• Filed: 10/12/2015
• Issued: 04/03/2018
• Est. Priority Date: 05/12/2010
• Status: Active Grant

• Current Assignee: FotoNation Limited (Adeia Inc.)
• Original Assignee: Fotonation Cayman Limited
• Inventors: McMahon, Andrew Kenneth John
• Primary Examiner(s): Tran, Nhan T
• Application Number:
  US14/880,907
• Publication Number:
  US 20160269627A1
• Time in Patent Office: 904 Days
• Field of Search: 348315, 348294, 348312, 348321, 348303, 3482181
• CPC Class Codes: H04N 23/13 with multiple sensors
• CPC Class Codes: H04N 23/951 by using two or more images to influence resolution, frame rate or aspect ratio
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
• CPC Class Codes: H04N 25/44 by partially reading an SSIS array
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image
• CPC Class Codes: H04N 25/704 Pixels specially adapted for focusing, e.g. phase difference pixel sets
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Architectures for imager arrays configured for use in array cameras in accordance with embodiments of the invention are described. One embodiment of the invention includes a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane, control circuitry configured to control the capture of image information by the pixels within the focal planes, where the control circuitry is configured so that the capture of image information by the pixels in at least two of the focal planes is separately controllable, sampling circuitry configured to convert pixel outputs into digital pixel data, and output interface circuitry configured to transmit pixel data via an output interface.

Claims

1. An imager array, comprising:

a plurality of cameras, where each camera comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each camera is contained within a region of the imager array that does not contain pixels from another camera;

control circuitry configured to capture image data using the plurality of cameras, wherein the control circuitry is configured to control the capture of the image data by the pixels within the cameras, where the control circuitry is configured so that the capture of image data by the pixels in at least two of the cameras is separately controllable;

master control logic circuitry configured to control the read-out of pixel data from the plurality of cameras by;

generating at least one line of image data by multiplexing said image data captured by said plurality of cameras;

generating additional data, where said additional data comprises information regarding operating parameters of said plurality of cameras and information for demultiplexing the captured plurality of images from the generated at least one line of image data;

packetizing said at least one line of image data and said additional data to produce at least one packet of data; and

output interface circuitry configured to transmit said at least one packet of data via an output interface.

2. The imager array of claim 1, wherein:

the imager array includes M×

N cameras;

the output interface includes less than M×

N output ports; and

the control circuitry is configured to time multiplex the at least one packet of data onto the output ports of the output interface.

3. The imager array of claim 1, wherein the control circuitry further comprises memory configured to buffer the at least one packet of data until a time-slot is available on an output port of the output interface to transmit the at least one packet of data.

4. The imager array of claim 1, wherein the additional data provides information identifying a camera.

5. The imager array of claim 1, wherein the additional data provides information identifying at least one row of pixels within a camera.

6. The imager array of claim 1, wherein the additional data provides information identifying at least one column of pixels within a camera.

7. The imager array of claim 1, wherein the additional data provides information identifying the relative time of image data capture.

8. The imager array of claim 7, wherein the additional data provides information identifying the relative start time of the image data capture.

9. The imager array of claim 7, wherein the additional data provides information identifying the relative end time of the image data capture.

10. The imager array of claim 7, wherein the control circuitry further comprises a counter and the additional data that provides information identifying the relative time of image data capture are generated using the counter.

11. The imager array of claim 1, wherein the additional data provides information concerning operating parameters of the imager array.

12. The imager array of claim 11, wherein the additional data provides the integration time of each camera.

13. The imager array of claim 11, wherein the additional data provides the gain of each camera.

14. The imager array of claim 1, wherein the output interface circuitry is configured to insert a frame blanking interval between transmission of the at least one packet of data via the output interface.

15. The imager array of claim 14, wherein the output interface circuitry is further configured to insert a line blanking interval between transmission of lines of image data via the output interface.

16. The imager array of claim 1, wherein the output interface circuitry is configured to transform the image data by performing bit reductions.

17. A method of obtaining pixel data, comprising:

separately capturing image data using an imager array having a plurality of cameras, wherein the capture of image data in at least two of the cameras is separately controllable, where each camera comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each camera is contained within a region of the imager array that does not contain pixels from another camera;

generating at least one line of image data by multiplexing said image data captured using the imager array having the plurality of cameras;

generating additional data, where said additional data comprises information regarding operating parameters of said plurality of cameras and information for demultiplexing the captured image data from the generated at least one line of image data;

packetizing said at least one line of image data and said additional data to produce at least one packet of data; and

transmitting the at least one packet of data via an output interface in the imager array.

18. The method of claim 17, where the additional data provides information identifying a camera.

19. The method of claim 17, where the additional data provides information identifying at least one row of pixels within a camera.

20. The method of claim 17, where the additional data provides information identifying at least one of:

at least one column of pixels within a camera;

the relative time of pixel data capture;

the relative start time of the pixel data capture;

the relative end time of the pixel data capture;

the integration time of each camera; and

the gain of each camera.