Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor

• US 9,939,879 B2
• Filed: 10/06/2015
• Issued: 04/10/2018
• Est. Priority Date: 10/27/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Rotem, Efraim, Rajwan, Doron, Shrall, Jeremy J., Samson, Eric C., Weissmann, Eliezer, Wells, Ryan
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US14/875,930
• Publication Number:
  US 20160026229A1
• Time in Patent Office: 917 Days
• Field of Search: 710300-340
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

Claims

1. A processor comprising:

a first domain having at least one core;

a second domain having at least one graphics processor; and

a power controller coupled to the first domain and the second domain, wherein the first domain is to operate in a frequency range between a maximum frequency and a guaranteed frequency, the maximum frequency and the guaranteed frequency set at manufacture, wherein the second domain is to request the power controller to dynamically reduce the frequency range of the first domain.

2. The processor of claim 1, wherein the dynamic reduction comprises a reduction of at least one of the maximum frequency and the guaranteed frequency.

3. The processor of claim 1, wherein the second domain is to issue the request to the power controller responsive to a determination that the second domain is in operation at a frequency less than a requested frequency.

4. The processor of claim 1, wherein responsive to the dynamic reduction of the frequency range of the first domain, the second domain is to receive a greater power budget.

5. The processor of claim 1, wherein the power controller comprises a power control unit included in the processor.

6. The processor of claim 1, wherein the processor comprises a first fuse to store the maximum frequency and a second fuse to store the guaranteed frequency.

7. The processor of claim 1, further comprising:

a shared cache memory coupled to the first domain and the second domain; and

a memory controller.

8. The processor of claim 3, wherein the second domain is to issue the request to the power controller when the second domain is to execute a particular workload.

9. The processor of claim 3, wherein the second domain is to update a first field of a configuration register if the second domain is in operation at the frequency less than the requested frequency.

10. The processor of claim 9, wherein the power controller is to limit the maximum frequency of the first domain based on the updated first field of the configuration register.

11. The processor of claim 10, wherein the second domain is to thereafter update a second field of the configuration register.

12. The processor of claim 11, wherein the power controller is to limit the guaranteed frequency of the first domain based on the updated second field of the configuration register.

13. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

determining that a first domain of a processor is not operating at a frequency requested by the first domain, the first domain comprising one or more graphics engines;

responsive to the determination, sending a request from the first domain to a power controller to reduce a frequency of a second domain of the processor, the second domain comprising one or more cores; and

responsive to the request, reducing the frequency of the second domain to allocate a greater power budget to the first domain, to enable an increase in the frequency of the first domain.

14. The machine-readable medium of claim 13, wherein the method further comprises:

updating a first field of a configuration register to cause the power controller to reduce a maximum turbo frequency of the second domain; and

updating a second field of the configuration register to cause the power controller to reduce a guaranteed frequency of the second domain.

15. The machine-readable medium of claim 13, wherein the method further comprises:

determining whether the second domain is operating at least at a guaranteed frequency; and

causing the guaranteed frequency of the second domain to be lowered from a fused value to a second guaranteed value less than the fused value.

16. A system comprising:

a processor including;

a first domain having one or more cores, the first domain to operate at a frequency range between a maximum frequency and a guaranteed frequency, the maximum frequency and the guaranteed frequency set at manufacture;

a second domain having at least one graphics engine;

a shared cache memory;

a memory controller; and

a power controller to receive a request from the second domain to dynamically reduce the frequency range at which the first domain can operate, responsive to a determination that the second domain is in operation at a frequency less than a requested frequency; and

a dynamic random access memory (DRAM) coupled to the processor.

17. The system of claim 16, wherein the power controller is to allocate a higher power budget to the second domain, to enable the second domain to operate at a higher frequency after the dynamic reduction in the first domain frequency range.

18. The system of claim 16, wherein the power controller is to first reduce the maximum frequency of the first domain, and to thereafter reduce the guaranteed frequency of the first domain if the second domain is not in operation at least at the requested frequency after the maximum frequency reduction.

19. The system of claim 16, wherein responsive to the dynamic reduction in the first domain frequency range, the power controller is to cause the first domain to operate at a frequency less than the guaranteed frequency, wherein the frequency less than the guaranteed frequency violates an operating system guaranteed frequency.

20. The system of claim 16, wherein the power controller comprises a frequency control logic to control a frequency of the first domain.