Voltage and frequency balancing at nominal point

• US 9,939,880 B1
• Filed: 07/26/2017
• Issued: 04/10/2018
• Est. Priority Date: 10/06/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Foreman, Eric A., Shuma, Stephen G.
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Desai, Sumil M
• Application Number:
  US15/659,775
• Publication Number:
  US 20180101212A1
• Time in Patent Office: 258 Days
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Claims

1. A method for determining voltage and frequency pairs, the method comprising:

computer processors identifying an integrated circuit design;

the computer processors identifying a timing model associated with the identified integrated circuit design;

the computer processors identifying at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design;

the computer processors receiving a number n that defines the number of at least one alternate voltage within the voltage range;

the computer processors analyzing the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range;

the computer processors performing a single statistical static timing analysis for the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range, wherein the single statistical static timing analysis calculates voltage sensitivity via finite differencing with respect to the identified timing model;

the computer processors creating a canonical variability of frequency dependent tests, wherein the clock period and voltage are parameterized;

the computer processors performing a multi-corner static timing analysis for the identified integrated circuit based on the received number n for each number n for the identified at least one alternate voltage within the voltage range;

the computer processors calculating a timing at a first voltage point and a timing second voltage point;

the computer processors calculating a sensitivity to voltage that is a difference between the timing at the first voltage point and the timing at a second voltage point;

the computer processors calculating a nominal slack;

the computer processors calculating one or more clock periods based on the calculated nominal slack;

the computer processors solving a slack equation for a clock period;

the computer processors calculating the clock period for each number n by inserting each calculated voltage for each number n into the solved slack equation for the clock period;

the computer processors providing a report based on the calculated one or more clock periods; and

the computer processors optimizing a voltage and frequency pairing for a best power-performance balance, wherein the voltage and frequency pairing meets a maximum power and a minimum frequency.