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Power management in a configurable bus

  • US 9,939,881 B2
  • Filed: 09/27/2013
  • Issued: 04/10/2018
  • Est. Priority Date: 09/17/2013
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • bus interface circuitry configured to interconnect to a bus; and

    a component, coupled to the bus interface circuitry, the component comprising circuitry configured to;

    responsive to a bus state of the bus, determine a period comprising a start and an end during which no data is sent to the component;

    upon detection of a cleared presence bit by the component, cause the component to enter a sleep mode during the period, the cleared presence bit indicating that no data is present for the component; and

    responsive to a set presence bit in a first received frame at the component, cause the component to initiate a waking process, the waking process comprising continually clearing a set value of a clear-to-send bit in a first sent frame until after the end of the period, the set presence bit indicating that there is data for the component; and

    after clearing the set value of the clear-to-send bit in the first sent frame, indicate that the period has completed and the waking process has completed by allowing the set value of the clear-to-send bit to remain set for a predetermined number of consecutive sent frames.

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