Power management in a configurable bus

• US 9,939,881 B2
• Filed: 09/27/2013
• Issued: 04/10/2018
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Sinha, Rajesh Kumar
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Wang, Zhipeng
• Application Number:
  US14/040,099
• Publication Number:
  US 20150082064A1
• Time in Patent Office: 1,656 Days
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: H04W 52/0251 using monitoring of local events, e.g. events related to user activity
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A system includes a bus and a component interconnected via the bus. The component may enter a sleep mode during a period of no data transmission involving the component.

Claims

1. A system, comprising:

bus interface circuitry configured to interconnect to a bus; and

a component, coupled to the bus interface circuitry, the component comprising circuitry configured to;

responsive to a bus state of the bus, determine a period comprising a start and an end during which no data is sent to the component;

upon detection of a cleared presence bit by the component, cause the component to enter a sleep mode during the period, the cleared presence bit indicating that no data is present for the component; and

responsive to a set presence bit in a first received frame at the component, cause the component to initiate a waking process, the waking process comprising continually clearing a set value of a clear-to-send bit in a first sent frame until after the end of the period, the set presence bit indicating that there is data for the component; and

after clearing the set value of the clear-to-send bit in the first sent frame, indicate that the period has completed and the waking process has completed by allowing the set value of the clear-to-send bit to remain set for a predetermined number of consecutive sent frames.

2. The system of claim 1, where the circuitry is further configured to determine the start of the period responsive to a clock pause sent over the bus.

3. The system of claim 2, where the component is configured to receive the clock pause in response to a completion of a data transmission.

4. The system of claim 1, where the circuitry is configured to determine the start of the period responsive to a flow control field, the flow control field included in a second received frame sent via the bus.

5. The system of claim 4, where:

the flow control field comprises the cleared presence bit; and

the second received frame comprises a SLIMbus-compliant message, the cleared presence bit configured to indicate the start of the period.

13. The system of claim 1, where the bus is configured to support burst-mode transfers.

14. The system of claim 13, where the period comprises a break in transmission created by opportunistic application of a burst-mode transfer.

15. The system of claim 1, where the bus is configured to support pushed digital audio transport to the component.

6. A method, comprising:

determining a period in which no data is sent to a component over a bus period responsive to an asserted presence bit in a first received frame;

upon detection of a presence bit being in a first state indicating that no data is present for the component, causing the component to enter a sleep mode during the period;

upon detection of the presence bit being in a second state indicating that there is data for the component, causing the component to initiate a waking process, the waking process comprising continually clearing a set value of a clear-to-send bit in a first sent frame until an end of the period; and

after clearing the set value of the clear-to-send bit in the first sent frame, indicating that the period has completed and the waking process has completed by allowing the set value of the clear-to-send bit to remain set for a predetermined number of consecutive sent frames.

7. The method of claim 6, where the bus period is for a bus and the bus comprises a configurable bus.

12. The method of claim 6, where determining the period comprises determining a start of the period responsive to a cleared presence bit within a second received frame.

16. The method of claim 6, requesting a bus clock rate increase to effect an opportunistic burst mode transfer that creates the period which no data is sent to the component.

17. The method of claim 6, where a start of the period comprises a completion of a pulled digital audio transport stream.

8. A product comprising:

a machine-readable medium other than a transitory signal; and

instructions stored on the machine-readable medium, the instructions, when executed, configured to cause a processor to;

determine a period in which no data is sent to a component over a bus;

upon detection of a cleared presence bit indicating that no data is present for the component, cause the component to enter a sleep mode during the period;

while the component is in the sleep mode, determine that the component is not ready to receive a transmission over the bus; and

responsive to an asserted presence bit in a first received frame indicating that there is data for the component, cause the component to initiate a waking process, the waking process comprising continually clearing a set value of a clear-to-send bit in a first sent frame; and

after clearing the set value of the clear-to-send bit in the first sent frame, indicating that the period has completed and the waking process has completed by allowing the set value of the clear-to-send bit to remain set for a predetermined number of consecutive sent frames.

9. The product of claim 8, where the instructions are further configured to cause the processor to determine a start of the period responsive to a clock pause sent over the bus.

10. The product of claim 9, where the instructions are further configured to cause the processor to receive the clock pause in response to a completion of a data transmission.

11. The product of claim 8, where the instructions are further configured to cause the processor to determine a start of the period responsive to the cleared presence bit within a second received frame.

18. The product of claim 8, where the component comprises an application processor coupled via the bus to audio circuitry, GPS circuitry, wireless networking circuitry, or any combination thereof.

19. The product of claim 8, where the instructions are further configured to cause the processor to request a bus clock rate increase to effect an opportunistic burst mode transfer that creates the period which no data is sent to the component.

20. The product of claim 8, where a start of the period comprises a completion of a pulled digital audio transport stream.