Supply-voltage control for device power management
First Claim
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1. A method for managing leakage current in logic, the method comprising:
- detecting an entry of a component into an idle period;
determining the duration of the idle period exceeds at least one of a first pre-determined inactivity threshold and a second pre-determined inactivity threshold, the second pre-determined inactivity threshold corresponding to a duration longer than a duration corresponding to the first pre-determined inactivity threshold;
in response to determining the duration of the idle period exceeds the first pre-determined inactivity threshold, selectively opening a first number of transistor switches from a plurality of transistor switches coupling a voltage source to a logic of component to achieve a first voltage level, the first voltage level being below an operational supply-voltage threshold and above a data-retention voltage threshold;
in response to determining the duration of the idle period exceeds the second pre-determined inactivity threshold, saving a logic state of the component, and selectively opening a second number of transistor switches from the plurality of transistor switches to achieve a second voltage level, the second voltage level being below the data-retention voltage threshold;
detecting an exit of the component from the idle period; and
in response to detecting an exit of the component from the idle period, selectively closing a third number of transistor switches to raise the supply-voltage of the component above the operational supply-voltage threshold,wherein the selectively opening and closing comprises selecting the first, second, and third number of transistor switches to distribute groups of closed switches substantially uniformly over the logic.
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Abstract
One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply-voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold.
155 Citations
20 Claims
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1. A method for managing leakage current in logic, the method comprising:
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detecting an entry of a component into an idle period; determining the duration of the idle period exceeds at least one of a first pre-determined inactivity threshold and a second pre-determined inactivity threshold, the second pre-determined inactivity threshold corresponding to a duration longer than a duration corresponding to the first pre-determined inactivity threshold; in response to determining the duration of the idle period exceeds the first pre-determined inactivity threshold, selectively opening a first number of transistor switches from a plurality of transistor switches coupling a voltage source to a logic of component to achieve a first voltage level, the first voltage level being below an operational supply-voltage threshold and above a data-retention voltage threshold; in response to determining the duration of the idle period exceeds the second pre-determined inactivity threshold, saving a logic state of the component, and selectively opening a second number of transistor switches from the plurality of transistor switches to achieve a second voltage level, the second voltage level being below the data-retention voltage threshold; detecting an exit of the component from the idle period; and in response to detecting an exit of the component from the idle period, selectively closing a third number of transistor switches to raise the supply-voltage of the component above the operational supply-voltage threshold, wherein the selectively opening and closing comprises selecting the first, second, and third number of transistor switches to distribute groups of closed switches substantially uniformly over the logic. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 20)
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11. A logic-device component exhibiting reduced leakage current, the component comprising:
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logic having an operational supply-voltage threshold for maintaining operation thereof and a data-retention supply-voltage threshold for retaining data; arranged in parallel, two or more transistor switches switchably coupling a voltage supply line to the logic, each switch comprising a respective gate terminal to control whether the switch is open or closed; and a power-management unit operatively coupled to the gate terminals of the switches and configured to;
determine a first number of switches to open or close to achieve a first voltage level between the operational supply-voltage and the data-retention supply-voltage and a second number of switches to open or close to achieve a second voltage level below the data-retention supply-voltage, selectively open or close one or more of the switches to lower a voltage supplied to the logic to the first voltage level after the logic enters an idle period exceeding a first inactivity threshold;
maintain the voltage above the data-retention supply-voltage threshold; and
after the idle period exceeds a second inactivity threshold, selectively open one or more of the switches to lower the voltage to the second voltage level,wherein the power-management unit selectively opens or closes the two or more transistor switches to distribute groups of closed switches substantially uniformly over the logic. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A logic-device component exhibiting reduced leakage current, the component comprising:
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logic having an operational supply-voltage threshold for maintaining operation thereof and a data-retention supply-voltage threshold for retaining data; distributed over the logic, two or more zones of transistor switches, the switches of each zone coupled in parallel with gate terminals coupled to a common control line, each zone switchably connecting a voltage supply line to a nearest region of the logic; and a power-management unit operatively coupled to the control line of each zone and configured to;
determine a first zone of switches from the two or more zones of transistor switches to open or close to achieve a first voltage level between the operational supply-voltage and the data-retention supply-voltage and a second zone of switches from the two or more zones of transistor switches to open or close to achieve a second voltage level below the data-retention supply-voltage, selectively open one or more of the zones of switches to lower a voltage supplied to the logic to the first voltage level after the logic enters an idle period exceeding a first inactivity threshold;
maintain the voltage above the data-retention supply-voltage threshold; and
after the idle period exceeds a second inactivity threshold, selectively open one or more of the zones of switches to lower the voltage to the second voltage levelwherein the power-management unit selectively opens or closes the two or more transistor switches to distribute groups of closed switches substantially uniformly over the logic. - View Dependent Claims (19)
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Specification