Data storage device and data maintenance method thereof

• US 9,940,058 B2
• Filed: 10/07/2016
• Issued: 04/10/2018
• Est. Priority Date: 02/17/2016
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Lee, Jie-Hao
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): VO, THANH DUC
• Application Number:
  US15/287,998
• Publication Number:
  US 20170235489A1
• Time in Patent Office: 550 Days
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.

Claims

1. A data storage device, comprising:

a flash memory, having a plurality of single-level cell (SLC)-spare blocks, a plurality of triple-level cell (TLC)-data blocks, and a plurality of TLC-spare blocks; and

a controller, equally distributing the TLC-data blocks into three regions having the same number of TLC-data blocks, and receiving a prewrite data sector and a logic address of the prewrite data sector, and obtaining a first sub-prewrite data sector, a second sub-prewrite data sector and a third sub-prewrite data sector according to the prewrite data sector and the logic address, wherein in a first stage, the controller further;

determining a first TLC-data block corresponding to the logic address of the prewrite data sector according to the logic address, defining the region that contains the first TLC-data block as a first region;

determining whether the first TLC-data block has valid data, selecting a TLC-data block with the lowest erase count from the first region to serve as a new first TLC-data block when the first TLC-data block has valid data;

selecting a second TLC-data block and a third TLC-data block from the regions other than the first region according to the new first TLC-data block;

respectively writing the first sub-prewrite data sector, the second sub-prewrite data sector and the third sub-prewrite data sector into the new first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode; and

mapping the first new TLC-data block, the second TLC-data block, the third TLC-data block to the logic address.

2. The data storage device as claimed in claim 1, wherein total number of the TLC-data blocks is N, each of the TLC-data blocks has an address, and the addresses of the TLC-data blocks are in sequence.

3. The data storage device as claimed in claim 2, wherein the controller further respectively defines the regions other than the first region as a second region and a third region, wherein the address of the new first TLC-data block plus N/3 is equal to the address of the second TLC-data block and the address of the new first TLC-data block plus (2N)/3 is equal to the address of the third TLC-data block when the addresses of the TLC-data blocks of the first region precede the addresses of the TLC-data blocks of the second region and the third region, the address of the new first TLC-data block plus N/3 is equal to the address of the second TLC-data block and the address of the new first TLC-data block subtract N/3 is equal to the address of the third TLC-data block when the addresses of the TLC-data blocks of the first region precede the addresses of the TLC-data blocks of the second region and are subsequent to the addresses of the TLC-data blocks of the third region, and the address of the new first TLC-data block subtract (2N)/3 is equal to the address of the second TLC-data block and the address of the new first TLC-data block subtract N/3 is equal to the address of the third TLC-data block when the addresses of the TLC-data blocks of the first region are subsequent to the addresses of the TLC-data blocks of the second region and the third region.

4. The data storage device as claimed in claim 1, wherein in a second stage, the controller further programs data in the new first TLC-data block, the second TLC-data block and the third TLC-data block into one of the TLC-spare blocks, wherein the controller further selects a first TLC-spare block from the TLC-spare blocks to program the data in the new first TLC-data block, the second TLC-data block and the third TLC-data block, which are mapped to the logic address, into the first TLC-spare block by a TLC storage mode, maps the programmed first TLC-spare block to the logic address, and releases the new first TLC-data block, the second TLC-data block and the third TLC-data block.

5. The data storage device as claimed in claim 4, wherein the first stage is Production Phase, the second stage, which is after the first stage, is Integration Phase, and the data storage device goes through a high-temperature soldering between the first stage and the second stage.

6. A data maintenance method, applied to a data storage device having a plurality of single-level cell (SLC)-spare block, a plurality of triple-level cell (TLC)-data blocks and a plurality of TLC-spare blocks, the data maintenance method comprising:

receiving a prewrite data sector and a logic address of the prewrite data sector, and obtaining a first sub-prewrite data sector, a second sub-prewrite data sector and a third sub-prewrite data sector according to the prewrite data sector and the logic address; and

writing the prewrite data sector into the data storage device according to the prewrite data sector and the logic address in a first stage, wherein the step of writing the prewrite data sector into the data storage device in the first stage further comprises;

equally distributing the TLC-data blocks into three regions, wherein the regions have the same number of TLC-data blocks;

determining a first TLC-data block corresponding to the logic address of the prewrite data sector according to the logic address, defining the region that contains the first TLC-data block as a first region;

determining whether the first TLC-data block has valid data;

selecting a TLC-data block with the lowest erase count from the first region to serve as a new first TLC-data block and selecting a second TLC-data block and a third TLC-data block from the regions other than the first region according to the new first TLC-data block when the first TLC-data block has valid data;

respectively writing the first sub-prewrite data sector, the second sub-prewrite data sector and the third sub-prewrite data sector into the new first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode; and

mapping the first new TLC-data block, the second TLC-data block, the third TLC-data block to the logic address.

7. The data maintenance method as claimed in claim 6, wherein total number of TLC-data blocks is N, each of the TLC-data blocks has an address, and the addresses of the TLC-data blocks are in sequence.

8. The data maintenance method as claimed in claim 7, wherein the regions other than the first region are respectively defined as a second region and a third region, wherein the address of the new first TLC-data block plus N/3 is equal to the address of the second TLC-data block and the address of the new first TLC-data block plus (2N)/3 is equal to the address of the third TLC-data block when the addresses of the TLC-data blocks of the first region precede the addresses of the TLC-data blocks of the second region and the third region, the address of the new first TLC-data block plus N/3 is equal to the address of the second TLC-data block and the address of the new first TLC-data block subtract N/3 is equal to the address of the third TLC-data block when the addresses of the TLC-data blocks of the first region precede the addresses of the TLC-data blocks of the second region and are subsequent to the addresses of the TLC-data blocks of the third region, and the address of the new first TLC-data block subtract (2N)/3 is equal to the address of the second TLC-data block and the address of the new first TLC-data block subtract N/3 is equal to the address of the third TLC-data block when the addresses of the TLC-data blocks of the first region are subsequent to the addresses of the TLC-data blocks of the second region and the third region.

9. The data maintenance method as claimed in claim 6, wherein in a second stage the data maintenance method further comprises:

programming data in the new first TLC-data block, the second TLC-data block and the third TLC-data block into one of the TLC-spare blocks, wherein the step of programming data in the new first TLC-data block, the second TLC-data block and the third TLC-data block into one of the TLC-spare blocks further comprises;

selecting a first TLC-spare block from the TLC-spare blocks;

programming the data in the new first TLC-data block, the second TLC-data block and the third TLC-data block, which are mapped to the logic address, into the first TLC-spare block by a TLC storage mode;

mapping the programmed first TLC-spare block to the logic address; and

releasing the new first TLC-data block, the second TLC-data block and the third TLC-data block.

10. The data maintenance method as claimed in claim 9, wherein the first stage is Production Phase, the second stage, which is after the first stage, is Integration Phase, and the data storage device goes through a high-temperature soldering event between the first stage and the second stage.