Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries

• US 9,940,242 B2
• Filed: 11/17/2014
• Issued: 04/10/2018
• Est. Priority Date: 11/17/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gschwind, Michael K., Salapura, Valentina
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US14/543,434
• Publication Number:
  US 20160139925A1
• Time in Patent Office: 1,240 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0886 Variable-length word access
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.

Claims

1. A processor, comprising:

a processor core; and

a memory coupled to the processor core, wherein the processor core is configured to;

examine instructions in an instruction stream of the processor to determine properties of the instructions;

in response to an instruction in the instruction stream being a boundary instruction that is a last instruction before a cache boundary, determining a last property of the last instruction;

in response to another instruction in the instruction stream being a boundary instruction that is a first instruction after the cache boundary, determining a first property of the first instruction; and

indicating the last property of the last instruction and the first property of the first instruction to facilitate decode-time instruction optimization grouping of the last instruction and the first instruction in a single decode-time instruction optimization group.

2. The processor of claim 1, wherein the processor core is further configured to:

in response to an instruction in the instruction stream not being a boundary instruction, indicate whether adjacent ones of the instructions should be grouped in a same decode-time instruction optimization group based on the properties.

3. The processor of claim 1, wherein the processor core is further configured to:

group the last instruction and the first instruction in the single decode-time instruction optimization group in response to the first and last properties being compatible.

4. The processor of claim 1, wherein the processor core is further configured to:

group the last instruction and the first instruction in the single decode-time instruction optimization group in response to the first and last properties being compatible and a feedback value generated by a feedback function indicating the single decode-time instruction optimization group has been historically beneficial in improving performance of the processor.

5. The processor of claim 1, wherein the first and last properties are associated with instruction classes.

6. The processor of claim 1, wherein the first and last properties are associated with instruction registers.

7. The processor of claim 1, wherein the first and last properties are associated with instruction registers and instruction classes.

8. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the processor is configured to;

examine instructions in an instruction stream of the processor to determine properties of the instructions;

in response to an instruction in the instruction stream not being a boundary instruction, indicating whether adjacent ones of the instructions should be grouped in a same decode-time instruction optimization group based on the properties, wherein the boundary instruction is a last instruction before a cache boundary or a first instruction after the cache boundary;

in response to an instruction in the instruction stream being the last instruction, determining a last property of the last instruction;

in response to another instruction in the instruction stream being the first instruction, determining a first property of the first instruction; and

indicating the last property of the last instruction and the first property of the first instruction to facilitate decode-time instruction optimization grouping of the last instruction and the first instruction in a single decode-time instruction optimization group.

9. The data processing system of claim 8, wherein the processor is further configured to:

group the last instruction and the first instruction in the single decode-time instruction optimization group in response to the first and last properties being compatible.

10. The data processing system of claim 8, wherein the processor is further configured to:

group the last instruction and the first instruction in the single decode-time instruction optimization group in response to the first and last properties being compatible and a feedback value generated by a feedback function indicating the decode-time instruction optimization group has been historically beneficial in improving performance of the processor.