Methods for reducing congestion region in layout area of IC
First Claim
1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:
- obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal;
identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region;
obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region, wherein the candidate position is disposed in a sparse region adjacent to the congestion region in the routing area;
moving the cell corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations and moving one of the first and second macro modules according to the moved cell, and simultaneously updating the placement and the routing paths according to the moved cell and the moved macro module; and
manufacturing the integrated circuit based on the updated placement and the updated routing paths,wherein the updated placement comprises a second signal path between the moved macro module and the other macro module for transmitting the specific signal, and the moved cell is located outside the congestion region,wherein the first signal path is removed from the updated placement so as to adjust the layout of the integrated circuit.
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Abstract
A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.
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Citations
16 Claims
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1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:
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obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal; identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region; obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region, wherein the candidate position is disposed in a sparse region adjacent to the congestion region in the routing area; moving the cell corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations and moving one of the first and second macro modules according to the moved cell, and simultaneously updating the placement and the routing paths according to the moved cell and the moved macro module; and manufacturing the integrated circuit based on the updated placement and the updated routing paths, wherein the updated placement comprises a second signal path between the moved macro module and the other macro module for transmitting the specific signal, and the moved cell is located outside the congestion region, wherein the first signal path is removed from the updated placement so as to adjust the layout of the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for reducing congestion regions in a layout of an integrated circuit, the method comprising:
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obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal; identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region; obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path of the congestion region, wherein the candidate position is disposed in a sparse region adjacent to the congestion region in the routing area; moving the cell corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations and moving one of the first and second macro modules according to the moved cell, and simultaneously updating the placement and the routing paths according to the moved cell and the moved macro module; and manufacturing the integrated circuit based on the updated placement and the updated routing paths, wherein the updated placement comprises a second signal path between the moved macro module and the other macro module for transmitting the specific signal, and the moved cell is located outside the congestion region, wherein the first signal path is removed from the updated placement so as to adjust the layout of the integrated circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification