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Methods for reducing congestion region in layout area of IC

  • US 9,940,422 B2
  • Filed: 06/18/2015
  • Issued: 04/10/2018
  • Est. Priority Date: 01/08/2015
  • Status: Active Grant
First Claim
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1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:

  • obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal;

    identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region;

    obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region, wherein the candidate position is disposed in a sparse region adjacent to the congestion region in the routing area;

    moving the cell corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations and moving one of the first and second macro modules according to the moved cell, and simultaneously updating the placement and the routing paths according to the moved cell and the moved macro module; and

    manufacturing the integrated circuit based on the updated placement and the updated routing paths,wherein the updated placement comprises a second signal path between the moved macro module and the other macro module for transmitting the specific signal, and the moved cell is located outside the congestion region,wherein the first signal path is removed from the updated placement so as to adjust the layout of the integrated circuit.

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