Methods for reducing congestion region in layout area of IC

• US 9,940,422 B2
• Filed: 06/18/2015
• Issued: 04/10/2018
• Est. Priority Date: 01/08/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Hsu, Chin-Hsiung, Yang, Chun-Chih
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US14/743,099
• Publication Number:
  US 20160203254A1
• Time in Patent Office: 1,027 Days
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.

Claims

1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:

obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal;

identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region;

obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region, wherein the candidate position is disposed in a sparse region adjacent to the congestion region in the routing area;

moving the cell corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations and moving one of the first and second macro modules according to the moved cell, and simultaneously updating the placement and the routing paths according to the moved cell and the moved macro module; and

manufacturing the integrated circuit based on the updated placement and the updated routing paths,

wherein the updated placement comprises a second signal path between the moved macro module and the other macro module for transmitting the specific signal, and the moved cell is located outside the congestion region,

wherein the first signal path is removed from the updated placement so as to adjust the layout of the integrated circuit.

2. The method as claimed in claim 1, wherein-the second signal path comprises the moved cell and the updated routing paths corresponding to the moved cell.

3. The method as claimed in claim 2, wherein the second signal path does not pass through the congestion region, and the first and second macro modules are arranged around the routing area.

4. The method as claimed in claim 1, further comprising:

dividing the routing area into a plurality of exploration regions; and

obtaining a cell density and a routing density of each of the exploration regions.

5. The method as claimed in claim 4, wherein the congestion region comprises the exploration regions having the cell density or the routing density greater than a specific density.

6. The method as claimed in claim 1, the step of obtaining the cost evaluation for each of the candidate positions of the routing area by moving the cell or the routing path out of the congestion region further comprises:

selecting one candidate position from the candidate positions;

obtaining a placement cost by moving the cell from the congestion region to the selected candidate position;

obtaining a routing cost by rerouting the routing paths corresponding to the cell moved to the selected candidate position; and

obtaining the cost evaluation for the selected candidate position according to the placement cost and the routing cost.

7. The method as claimed in claim 6, wherein the routing area is divided into a plurality of exploration regions, and the placement cost comprises a cell density of the exploration region that the selected candidate position is located, and the routing cost comprises a routing density of the exploration region where the selected candidate position is located.

8. The method as claimed in claim 1, wherein positions of the first macro module and the second macro module in the placement are different from the positions of the first macro module and the second macro module in the updated placement.

9. The method as claimed in claim 8, wherein the positions of the first macro module and the second macro module in the updated placement are arranged in a straight line.

10. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for reducing congestion regions in a layout of an integrated circuit, the method comprising:

obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal;

identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region;

obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path of the congestion region, wherein the candidate position is disposed in a sparse region adjacent to the congestion region in the routing area;

moving the cell corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations and moving one of the first and second macro modules according to the moved cell, and simultaneously updating the placement and the routing paths according to the moved cell and the moved macro module; and

manufacturing the integrated circuit based on the updated placement and the updated routing paths,

wherein the updated placement comprises a second signal path between the moved macro module and the other macro module for transmitting the specific signal, and the moved cell is located outside the congestion region,

wherein the first signal path is removed from the updated placement so as to adjust the layout of the integrated circuit.

11. The non-transitory computer-readable storage medium as claimed in claim 10, wherein the second signal path comprises the moved cell and the updated routing paths corresponding to the moved cell.

12. The non-transitory computer-readable storage medium as claimed in claim 10, the method further comprising:

dividing the routing area into a plurality of exploration regions; and

obtaining a cell density and a routing density of each of the exploration regions.

13. The non-transitory computer-readable storage medium as claimed in claim 10, the step of obtaining the cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region further comprises:

selecting one candidate position from the candidate positions;

obtaining a placement cost by moving the cell from the congestion region to the selected candidate position;

obtaining a routing cost by rerouting the routing paths corresponding to the cell moved to the selected candidate position; and

obtaining the cost evaluation for the selected candidate position according to the placement cost and the routing cost.

14. The non-transitory computer-readable storage medium as claimed in claim 13, wherein the routing area is divided into a plurality of exploration regions, and the placement cost comprises a cell density of the exploration region that the selected candidate position is located, and the routing cost comprises a routing density of the exploration region where the selected candidate position is located.

15. The non-transitory computer-readable storage medium as claimed in claim 10, wherein positions of the first macro module and the second macro module in the placement are different from the positions of the first macro module and the second macro module in the updated placement.

16. The method as claimed in claim 15, wherein the positions of the first macro module and the second macro module in the updated placement are arranged in a straight line.