Display systems with compensation for line propagation delay

• US 9,940,861 B2
• Filed: 07/13/2017
• Issued: 04/10/2018
• Est. Priority Date: 05/23/2012
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza, Azizi, Yaser
• Primary Examiner(s): Edun, Muhammad N
• Application Number:
  US15/649,065
• Publication Number:
  US 20170309210A1
• Time in Patent Office: 271 Days
• CPC Class Codes: G09G 1/002 Intensity circuits G09G1/06 - G09G1/28 take precedence
• CPC Class Codes: G09G 1/12 the deflection signals being produced by essentially analogue means
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 2330/10 Dealing with defective pixels
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/18 using liquid crystals
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A method for characterizing and eliminating the effect of propagation delay on data and monitor lines of AMOLED panels is introduced. A similar technique may be utilized to cancel the effect of incomplete settling of select lines that control the write and read switches of pixels on a row.

Claims

1. A display comprising:

a plurality of pixel circuits;

a driver for programming the pixel circuits;

a monitor for monitoring the pixel circuits;

a signal line connecting the pixel circuits with at least one of the driver and the monitor;

a memory including propagation delay effects information for at least a subset of the pixel circuits to compensate for parasitic effects in the signal line; and

a controller capable of controlling the pixel circuit, and at least one of the driver and the monitor;

wherein the controller is capable of controlling the pixel circuit based on the propagation delay effects information stored in the memory.

2. The display according to claim 1, wherein the propagation delay effects information comprises signal offsets of signals on the signal line.

3. The display according to claim 2, wherein the controller is further capable of updating the propagation delay effects by:

generating a first signal from a first position on the signal line;

measuring a first signal level at a second position on the signal line upon expiry of a first time duration sufficient to avoid settling effects;

generating a second signal from the first location;

measuring a second signal level at the second location upon expiry of a second time duration insufficient to avoid settling effects; and

comparing the first signal level with the second signal level to extract the signal offset of signals on the signal line.

4. The display according to claim 3, wherein the controller is capable of determining a gain factor associated with current measured from each pixel based on a ratio of the measured first and second signal values;

and scale a subsequent current measurement according to the determined gain factor so as to account for the propagation delay effects of the monitoring line.

5. The display according to claim 3, wherein the plurality of pixels comprises an array of pixel circuits arranged in rows and columns, and wherein the controller is further configured to repeat the measurement and comparison for the subset of the pixels in the display so as to characterize the propagation delay effects of the monitoring line at a range of line distances from the monitor.

6. The display of claim 3, wherein the controller is also capable of varying the at least one of the first time duration and the second time duration as a function of a physical distance between the first location and the second location.

7. The display of claim 3, wherein the controller is further capable of controlling the monitor to, prior to the controller'"'"'s comparing the first signal measurement with the second signal measurement:

extract the first signal measurement from the second location over a monitor line after the expiry of the first time duration and after sufficient monitoring time to avoid settling effects on the monitor line; and

extract the second signal measurement from the second location over the monitor line after the expiry of the second time duration and after sufficient monitoring time to avoid settling effects on the monitor line,

and wherein the controller is further capable of controlling the pixel circuit to;

perform said measuring of the first signal at the second location by storing a measured level of the first signal at the pixel circuit upon expiry of the first time duration; and

perform said measuring of the second signal at the second location by storing a measured level of the second signal at the pixel circuit upon expiry of the second time duration.

8. The display of claim 2, wherein the signal offset comprises a voltage signal offset, and the first and second signals comprise voltage signals.

9. The display of claim 2, wherein the signal offset comprises a current signal offset, and the first and second signals comprise current signals.

10. The display of claim 2, wherein the signal line comprises a data line connected to the pixel circuit at the second location and connected to the driver at the first location, the signal offset comprises a programming signal offset, and the first and second signals are programming signals transmitted to the pixel circuit.

11. The display of claim 2, wherein the signal line comprises a monitor line connected to the pixel circuit at the first location and connected to the monitor at the second location, the signal offset comprises a monitored signal offset, and the first and second signals are monitored signals received from the pixel circuit.

12. The display of claim 1, wherein the controller is capable of extracting the propagation delay effects information during an initial factory calibration.

13. The display of claim 1, wherein the controller is further capable of calibrating at least one of programming of the pixel circuit and monitoring of the pixel circuit with use of the propagation delay effects information.

14. The display according to claim 1, wherein the memory further comprises a calibration value for each of the subset of pixels;

wherein the controller is capable of compensating for at least one of pixel aging and pixel non-uniformity using the calibration values; and

wherein the controller is capable of scaling the calibration values based on the propagation delay effects information.