High-speed word line decoder and level-shifter
First Claim
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1. A circuit, comprising:
- a first logic gate configured to discharge a word line driver node responsive to an assertion of a first plurality of decoded signals to a first power supply voltage;
a word line;
an inverter powered by a second power supply voltage, wherein the inverter is configured to invert a voltage of the word line driver node into a word line voltage for the word line;
a switch coupled between a power supply input node to the first logic gate and a power supply node for the second power supply voltage; and
a second logic gate configured to switch off the switch responsive to the discharge of the word line driver node and a discharge of a complement of one of the decoded signals in the first plurality of decoded signals, wherein the second power supply voltage is greater than the first power supply voltage.
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Abstract
A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter'"'"'s unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.
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Citations
19 Claims
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1. A circuit, comprising:
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a first logic gate configured to discharge a word line driver node responsive to an assertion of a first plurality of decoded signals to a first power supply voltage; a word line; an inverter powered by a second power supply voltage, wherein the inverter is configured to invert a voltage of the word line driver node into a word line voltage for the word line; a switch coupled between a power supply input node to the first logic gate and a power supply node for the second power supply voltage; and a second logic gate configured to switch off the switch responsive to the discharge of the word line driver node and a discharge of a complement of one of the decoded signals in the first plurality of decoded signals, wherein the second power supply voltage is greater than the first power supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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in a first power domain powered by a first power supply voltage, decoding an address signal to assert a plurality of decoded signals to the first power supply voltage; in a second power domain powered by a second power supply voltage, discharging a word line driver node responsive to the assertion of the plurality of decoded signals while opening a switch to isolate the word line driver node from a power supply node supplying the second power supply voltage; responsive to the discharge of the word line driver node, charging a voltage for a word line in the second power domain to the second power supply voltage; and responsive to a discharge of at least one of the decoded signals in the plurality of decoded signals, closing the switch and charging the word line driver node to the second power supply voltage, wherein the second power supply voltage is greater than the first power supply voltage. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A memory, comprising:
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a row decoder configured to decode a plurality of address signals to produce a plurality of decoded signals, wherein the row decoder is in a first power domain powered by a first power supply voltage; a NAND gate configured to NAND the plurality of decoded signals to produce a NAND gate output signal, wherein the NAND gate is in a second power domain powered by a second power supply voltage, wherein the second power supply voltage is greater than the first power supply voltage; means for isolating the NAND gate from the second power supply voltage responsive to a reset of one of the decoded signals in the plurality of decoded signals and for coupling the NAND gate to the second power supply voltage responsive to an assertion of the one of the decoded signals; a word line; and a word line driver configured to assert a voltage of the word line to the second power supply voltage responsive to a discharge of the NAND gate output signal. - View Dependent Claims (18, 19)
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Specification