Memory device and memory system performing request-based refresh, and operating method of the memory device

• US 9,940,991 B2
• Filed: 11/04/2016
• Issued: 04/10/2018
• Est. Priority Date: 11/06/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyun-Joong, Song, Ho-young, Chung, Hoi-ju, Jung, Ju-yun, Cha, Sang-uhn
• Primary Examiner(s): DINH, SON T
• Application Number:
  US15/343,977
• Publication Number:
  US 20170133085A1
• Time in Patent Office: 522 Days
• Field of Search: 365222, 365236
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2211/4068 Voltage or leakage in refresh operations
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Claims

1. An operating method of a memory device, the operating method comprising:

determining, by the memory device, a weak row based on a counting of an activated number of at least one row;

outputting, to a memory controller, a request for refresh on the weak row based on a result of the determining;

receiving, from the memory controller, a refresh command in response to the request for the refresh; and

performing request-based refresh on the weak row in response to the receiving of the refresh command.

2. The operating method of claim 1, wherein the determining the weak row comprises:

counting an activated number of a first row; and

determining a second row adjacent to the first row as the weak row based on a result of the counting.

3. The operating method of claim 2, wherein the second row is determined as the weak row when the activated number of the first row is equal to or higher than a set value.

4. The operating method of claim 3, wherein the performing the request-based refresh further comprises:

performing the request-based refresh on the second row before the activated number of the first row exceeds the set value,

wherein a limit value of the activated number of the first row, which causes data of the second row to be lost, is pre-defined by a specification.

5. The operating method of claim 1, further comprising:

determining a refresh state of the weak row; and

determining a refresh condition of the weak row based on a result of the determined refresh state,

wherein the request for the refresh is selectively output based on the refresh condition.

6. The operating method of claim 5, wherein the determining the refresh condition comprises:

comparing a point of time when the weak row is last refreshed with a set value.

7. The operating method of claim 1, further comprising:

determining a refresh state of the memory device; and

determining a refresh condition of the weak row based on the refresh state of the memory device,

wherein the request for the refresh is selectively output based on the refresh condition.

8. The operating method of claim 7, wherein the determining the refresh condition comprises:

determining a number of refresh commands provided to the memory device during a certain interval.

9. The operating method of claim 1, further comprising:

communicating command, address, and data signals between the memory device and the memory controller through a plurality of channels; and

outputting the request for the refresh to the memory controller through a side channel different from the plurality of channels for communicating the command, the address, and the data signals.

10. The operating method of claim 1, further comprising:

communicating command, address, and data signals between the memory device and the memory controller through a plurality of channels; and

outputting the request for the refresh to the memory controller through one of the plurality of channels related to communicating the command, the address, and the data signals when the memory device is in a busy state.

11. The operating method of claim 1, wherein determining the weak row comprises:

counting an activated number of a first row; and

detecting at least two weak rows according to a result of the counting of the activated number,

wherein the at least two weak rows are sequentially refreshed in response to the refresh command.

12. An operating method of a memory system comprising a memory controller, the operating method comprising:

generating, by the memory controller, a first command related to writing and reading;

receiving, from a memory device, a request signal for requesting to output a refresh command;

generating, by the memory controller, a second command related to request-based refresh in response to the request signal; and

outputting, to the memory device, the second command based on scheduling of the first and second commands.

13. The operating method of claim 12, further comprising:

storing a plurality of first commands in a command queue; and

storing the second command in the command queue with the first commands after the plurality of the first commands are stored in the command queue,

wherein the second command is output before at least one of the plurality of first commands based on the scheduling.

14. The operating method of claim 12, wherein the memory system further comprises a memory device and the memory device comprises a plurality of rows, and

the operating method further comprises:

determining existence of conditions for performing request-based refresh on at least one row; and

generating the request signal based on the determining.

15. The operating method of claim 14, wherein the determining the existence of the conditions comprises:

counting an activated number of a first row from among the plurality of rows;

detecting at least one second row adjacent to the first row as a weak row based on a result of the counting; and

determining a refresh state of the second row.

16. The operating method of claim 15, wherein the request signal is generated when a point of time when the second row is last refreshed is before a set value indicating a certain point of time.

17. A memory device comprising:

a memory cell array comprising a plurality of rows;

a refresh controller configured to control a refresh operation on the plurality of rows; and

control logic configured to determine existence of conditions for performing request-based refresh on the at least one row during operation of the memory device, and output a request signal for requesting a refresh command based on the determining the existence of the conditions.

18. The memory device of claim 17, wherein the control logic comprises:

a weak row detector configured to detect at least one second row adjacent to a first row as a weak row when an activated number of the first row is equal to or higher than a set value; and

a refresh state determiner configured to determine the performance of request-based refresh on the second row based on a result of determining a refresh state of the second row.

19. The memory device of claim 18, wherein the control logic further comprises a request signal generator configured to generate the request signal according to a result of the determining,

wherein the refresh controller is further configured to perform refresh on the at least one second row in response to a refresh command received according to the request signal.

20. The memory device of claim 18, wherein the weak row detector comprises a comparator configured to compare a result of counting the activated number of the first row and the set value and generate a comparison result.