Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits

• US 9,940,999 B2
• Filed: 05/05/2017
• Issued: 04/10/2018
• Est. Priority Date: 06/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Lam, David
• Application Number:
  US15/587,947
• Publication Number:
  US 20170372777A1
• Time in Patent Office: 340 Days
• Field of Search: 365154, 36518914, 36518909, 365226
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method can of operating a semiconductor device can include generating a read or write assist signal having an enable logic level in response to a power supply potential being in a first voltage window and a disable logic level in response to the power supply potential being in a second voltage window. Access operations to a static random access memory (SRAM) cell can be altered in response to the assist signal having the assist enable logic level. The second voltage window can be larger than the first voltage window.

Claims

1. A method of operating a semiconductor device that is powered by a first power supply potential, including:

generating at least one read assist signal having a read assist enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window, and generating the at least one read assist signal having a read assist disable logic level in response to the voltage window detection circuit indicating the first power supply potential is in a second voltage window, and altering a read operation from a static random access memory (SRAM) cell to improve reliability when the at least one read assist signal has the read assist enable logic level;

wherein the second voltage window is larger than the first voltage window.

2. The method of claim 1, further including:

generating a word line potential that is less than the first power supply potential in response to the read assist signal having the read assist enable logic level, wherein the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the read operation.

3. The method of claim 2, wherein:

the step of generating the word line potential includes generating the word line potential that is less than the first power supply potential in response to the read assist signal and a read signal, the read signal indicates that data from the SRAM cell is to be accessed.

4. The method of claim 1, further including:

enabling a threshold voltage compensation circuit in response to the read assist signal having the read assist enable logic level;

wherein

the threshold voltage compensation circuit is included in a sense amplifier circuit and configured to compensate for differences in threshold voltages in a first insulated gate field effect transistor (IGFET) and a second IGFET during the read operation.

5. The method of claim 4, wherein:

the step of enabling the threshold compensation circuit includes disabling the threshold compensation circuit in response to the read assist signal having the read assist disable logic level.

6. The method of claim 1, wherein:

the semiconductor device includes a processor circuit portion and an SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.

7. The method of claim 6, wherein:

the processor circuit portion and the SRAM circuit portion are connected by a bus for transferring data between the processor circuit portion and the SRAM circuit portion.

8. A method of operating a semiconductor device that is powered by a first power supply potential, including:

generating at least one write assist signal having a write assist enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window, and generating the at least one write assist signal having a write assist disable logic level in response to the voltage window detection circuit indicating the first power supply potential is in a second voltage window, and altering a write operation to a static random access memory (SRAM) cell to improve reliability when the at least one write assist signal has the write assist enable logic level as compared to when the at least one write assist signal has the write disable logic level;

wherein the second voltage window is larger than the first voltage window.

9. The method of claim 8, further including:

the first power supply potential provides an upper power rail to the semiconductor device and a reference potential provides a lower power rail to the semiconductor device;

a first bit line and a second bit line are connected to the SRAM cell;

generating a write potential that is less than the reference potential in response to the write assist signal having the write assist enable logic level; and

driving essentially the write potential on one of the first or the second bit lines during the write operation.

10. The method of claim 9, wherein:

the step of generating the write potential includes generating the write potential that is essentially the reference potential in response to the write assist signal having the write assist disable logic level.

11. The method of claim 8, further including the step of:

generating a word line potential that is greater than the first power supply potential in response to the write assist signal having the write assist logic level;

wherein

the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the write operation.

12. The method of claim 11, wherein:

the step of generating the word line potential includes generating the word line potential that is essentially the same potential as the first power supply potential when the write assist signal has the write assist disable logic level.

13. The method of claim 8, further including the step of:

generating a cell power supply potential that is less than the first power supply potential in response to the write assist signal having the write assist enable logic level;

wherein

the SRAM cell is coupled to receive, and is powered by, the cell power supply potential.

14. The method of claim 13, wherein:

the step of generating the cell power supply potential includes generating the cell power supply potential that is essentially the same potential as the first power supply potential when the write assist signal has the write assist disable logic level.

15. The method of claim 8, wherein:

the semiconductor device includes a processor circuit portion and an SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.

16. The method of claim 15, wherein:

the processor circuit portion and the SRAM circuit portion are connected by a bus for transferring data between the processor circuit portion and the SRAM circuit portion.

17. A method, comprising:

determining if a power supply potential of a semiconductor device is within at least one of a plurality of voltage windows with a voltage window detection circuit on the semiconductor device;

enabling an assist signal if the power supply potential is determined to be in a first voltage window;

disabling the assist signal if the power supply potential is determined to be in a second voltage window; and

varying access operations to at least one static random access memory (SRAM) cell according to whether the assist signal is enabled or disabled;

wherein

the second voltage window is larger than the first voltage window.

18. The method of claim 17, wherein:

the access operations include read operations to the at least one SRAM cell; and

varying access operations is selected from the group of;

lowering a word line voltage when the assist signal is enabled as compared to when the assist signal is disabled, and

enabling a threshold voltage compensation circuit when the assist signal is enabled and disabling the threshold voltage compensation circuit when the assist signal is disabled;

wherein

the at least one SRAM cell includes an insulated gate field effect transistor (IGFET) having a gate connected to receive the word line voltage, and

the threshold voltage compensation circuit is part of a sense amplifier circuit that senses a data value stored by the at least one SRAM cell, the threshold voltage compensation circuit configured to compensate for threshold voltage differences in matching sense IGFETs of the sense amplifier circuit.

19. The method of claim 17, wherein:

the access operations include write operations to the at least one SRAM cell; and

varying access operations is selected from the group of;

increasing a write voltage when the assist signal is enabled as compared to when the assist signal is disabled, and

increasing a word line voltage when the assist signal is enabled as compared to when the assist signal is disabled, and

decreasing a cell power supply voltage when the assist signal is enabled as compared to when the assist signal is disabled;

wherein

the write voltage is applied to the at least one SRAM cell to store a data value therein, and

the at least one SRAM cell includes an insulated gate field effect transistor (IGFET) having a gate connected to receive the word line voltage, and is coupled to receive, and powered by, the cell power supply voltage.

20. The method of claim 17, wherein:

varying access operations further includes varying accesses by a processor circuit portion to the at least one SRAM cell over a bus;

wherein

the at least one SRAM cell and processor circuit portion are portions of the semiconductor device.