Memory array with one shared deep doped region

• US 9,941,011 B2
• Filed: 11/16/2016
• Issued: 04/10/2018
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lai, Tsung-Mu, Ching, Wen-Hao, Po, Chen-Hao
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Chen, Xiaochun L
• Application Number:
  US15/352,609
• Publication Number:
  US 20170206968A1
• Time in Patent Office: 510 Days
• Field of Search: 36518526
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Claims

1. A memory array comprising:

a plurality of memory pages, each memory page comprising a plurality of memory cells, and each memory cell comprising;

a floating gate module comprising a floating gate transistor, and configured to control the floating gate transistor according to a source line, a bit line and a word line, the floating gate transistor having a first terminal, a second terminal and a floating gate;

a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and

an erase element having a body terminal configured to receive a first voltage during a program operation and a program inhibit of the memory cell and receive a second voltage during an erase operation of the memory cell, a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element or being floating, and a control terminal coupled to the floating gate;

wherein;

the floating gate module is disposed in a first well;

the erase element is disposed in a second well;

the control element is disposed in a third well;

the first well, the second well and the third well are disposed in a deep doped region;

memory cells of the plurality of memory pages are all disposed in the deep doped region;

the control line is at the first voltage during the program operation;

the erase line is at the second voltage during the erase operation; and

control elements of the memory cells in a same memory page are disposed in the same third well.

2. The memory array of claim 1, wherein:

memory cells in a same memory page are coupled to a same control line, a same erase line, and a same word line; and

the memory cells in the same memory page are coupled to different source lines and different bit lines.

3. The memory array of claim 1, wherein the floating gate module further comprises:

a source transistor having a first terminal coupled to the source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to the word line; and

a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to the bit line, and a control terminal coupled to the word line.

4. The memory array of claim 1, wherein:

the deep doped region is a deep N-well or an N-type buried layer;

the first well and the third well are P-wells disposed in the deep doped region; and

the second well is an N-well disposed in the deep doped region.