Twin memory cell interconnection structure

• US 9,941,012 B2
• Filed: 03/08/2017
• Issued: 04/10/2018
• Est. Priority Date: 05/11/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: La Rosa, Francesco, Niel, Stephan, Regnier, Arnaud
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Chen, Xiaochun L
• Application Number:
  US15/453,663
• Publication Number:
  US 20170178733A1
• Time in Patent Office: 398 Days
• Field of Search: 36518518
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

Claims

1. A non-volatile memory, comprising:

a first twin pair of memory cells, the first twin pair including first and second memory cells arranged in a first column, the first and second memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the first twin pair having respective gate terminals coupled to one another;

a second twin pair of memory cells, the second twin pair including third and fourth memory cells arranged in a second column, the third memory cell being adjacent to the first memory cell, the fourth memory cell being adjacent to the second memory cell, the third and fourth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the second twin pair having respective gate terminals coupled to one another;

a first bitline coupled to a conduction terminal of the floating gate transistor of the first memory cell;

a second bitline coupled to a conduction terminal of the floating gate transistor of the second memory cell;

a third bitline coupled to a conduction terminal of the floating gate transistor of the third memory cell;

a fourth bitline coupled to a conduction terminal of the floating gate transistor of the fourth memory cell, the first, second, third, and fourth bitlines being different from one another; and

a first word line coupled to the gate terminals of the selection transistors of the first and second twin pairs.

2. The non-volatile memory of claim 1, comprising:

a third twin pair of memory cells, the third twin pair including fifth and sixth memory cells arranged in the first column, the fifth and sixth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the third twin pair having respective gate terminals coupled to one another;

a fourth twin pair of memory cells, the fourth twin pair including seventh and eighth memory cells arranged in the second column, the seventh memory cell being adjacent to the fifth memory cell, the eighth memory cell being adjacent to the sixth memory cell, the seventh and eighth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the fourth twin pair having respective gate terminals coupled to one another; and

a second word line coupled to the gate terminals of the selection transistors of the third and fourth twin pairs,

wherein the first bitline is coupled to a conduction terminal of the floating gate transistor of the sixth memory cell, the second bitline is coupled to a conduction terminal of the floating gate transistor of the fifth memory cell, the third bitline is coupled to a conduction terminal of the floating gate transistor of the eighth memory cell and the fourth bitline is coupled to a conduction terminal of the floating gate transistor of the seventh memory cell.

3. The non-volatile memory of claim 2 comprising:

a first gate control line coupled to respective control gates of the floating gate transistors of the first and third memory cells;

a second gate control line coupled to respective control gates of the floating gate transistors of the second and fourth memory cells;

a third gate control line coupled to respective control gates of the floating gate transistors of the fifth and seventh memory cells; and

a fourth gate control line coupled to respective control gates of the floating gate transistors of the sixth and eighth memory cells.

4. The non-volatile memory of claim 2, wherein the first, second and third bitlines are arranged over the first column of memory cells, and the fourth bitline is arranged over the second column of memory cells.

5. The non-volatile memory of claim 2, comprising:

an electrically isolating layer between the memory cells and the first through fourth bitlines;

a first conductive path coupling the first bitline to the conduction terminals of the floating gate transistors of the first and sixth memory cells, the first conductive path being routed through at least a portion of the electrically isolating layer;

a second conductive path coupling the second bitline to the conduction terminals of the floating gate transistors of the second and fifth memory cells, the second conductive path being routed through at least a portion of the electrically isolating layer;

a third conductive path coupling the third bitline to the conduction terminals of the floating gate transistors of the third and eighth memory cells, the third conductive path being routed through at least a portion of the electrically isolating layer; and

a fourth conductive path coupling the fourth bitline to the conduction terminals of the floating gate transistors of the fourth and seventh memory cells, the fourth conductive path being routed through at least a portion of the electrically isolating layer.

6. The non-volatile memory of claim 5, the electrically isolating layer comprising first, second, third, fourth and fifth isolating layers, wherein:

the first bitline extends over the second isolating layer;

the second bitline extends over the third isolating layer;

the third bitline extends over the fifth isolating layer; and

the fourth bitline extends over the fifth isolating layer.

7. The non-volatile memory according of claim 6, the first conductive path comprising:

a first via extending through the first isolating layer;

a first section of conductive line positioned on the first isolating layer and extending in a direction parallel to the first column of memory cells; and

a second via extending through the second isolating layer.

8. The non-volatile memory of claim 6, the second conductive path comprising:

a first via extending through the first isolating layer;

a first section of conductive line positioned on the first isolating layer and extending in a direction transverse to the first and second columns of memory cells;

a second via extending through the second isolating layer;

a second section of conductive line positioned on the second isolating layer and extending in a direction parallel to the second column of memory cells;

a third via extending through the third isolating layer; and

a third section of conductive line positioned on the third isolating layer and extending in a direction transverse to the first and second columns of memory cells.

9. The non-volatile memory of claim 6, the third conductive path comprising:

a first via extending through the first isolating layer,

a first section of conductive line positioned on the first isolating layer and extending in a direction parallel to the second column of memory cells;

a second via extending through the second isolating layer;

a second section of conductive line positioned on the second isolating layer and extending in a direction parallel to the second column of memory cells;

a third via extending through the third isolating layer;

a third section of conductive line positioned on the third isolating layer and extending in a direction parallel to the second column of memory cells;

a fourth via extending through the fourth isolating layer;

a fourth section of conductive line positioned on the fourth isolating layer and extending in a direction transverse to the first and second columns of memory cells; and

a fifth via extending through the fifth isolating layer.

10. The non-volatile memory of claim 6, the fourth conductive path comprising:

a first via extending through the first isolating layer;

a first section of conductive line positioned on the first isolating layer and extending in a direction parallel to the second column of memory cells;

a second via extending through the second isolating layer;

a second section of conductive line positioned on the second isolating layer and extending in a direction parallel to the second column of memory cells;

a third via extending through the third isolating layer;

a third section of conductive line positioned on the third isolating layer and extending in a direction parallel to the second column of memory cells;

a fourth via extending through the fourth isolating layer;

a fourth section of conductive line positioned on the fourth isolating layer and extending in a direction transverse to the first and second columns of memory cells; and

a fifth via extending through the fifth isolating layer.

11. The non-volatile memory of claim 1, further comprising a reading circuit and a column decoder, the reading circuit and column decoder being configured to read the memory cells.

12. A method, comprising:

forming first and second memory cells in a first column, the first and second memory cells each including a respective selection transistor and a respective floating gate transistor;

coupling respective gate terminals of the selection transistors of the first and second memory cells to one another;

forming third and fourth memory cells in a second column, adjacent to the first column, the third and fourth memory cells each including a respective selection transistor and a respective floating gate transistor;

coupling respective gate terminals of the selection transistors of the third and fourth memory cells to one another;

forming first, second, third and fourth bitlines, the first, second, third and fourth bitlines being different from one another;

coupling the first bitline to a conduction terminal of the floating gate transistor of the first memory cell;

coupling the second bitline to a conduction terminal of the floating gate transistor of the second memory cell;

coupling the third bitline to a conduction terminal of the floating gate terminal of the third memory cell; and

coupling the fourth bitline to a conduction terminal of the floating gate transistor of the fourth memory cell.

13. The method of claim 12, further comprising:

coupling a first word line to the gate terminals of the selection transistors of the first, second, third and fourth memory cells.

14. The method of claim 13, further comprising:

forming fifth and sixth memory cells in the first column, the fifth and sixth memory cells each including a respective selection transistor and a respective floating gate transistor, the fifth memory cell being adjacent to the second memory cell in the first column;

coupling respective gate terminals of the selection transistors of the fifth and sixth memory cells to one another;

forming seventh and eight memory cells in the second column, the seventh and eighth memory cells each including a respective selection transistor and a respective floating gate transistor, the seventh memory cell being adjacent to the fourth memory cell in the second column;

coupling respective gate terminals of the selection transistors of the seventh and eighth memory cells to one another;

coupling the first bitline to a conduction terminal of the floating gate transistor of the sixth transistor;

coupling the second bitline to a conduction terminal of the floating gate transistor of the fifth memory cell;

coupling the third bitline to a conduction terminal of the floating gate transistor of the eighth memory cell;

coupling the fourth bitline to a conduction terminal of the floating gate transistor of the seventh memory cell; and

coupling a second word line to the gate terminals of the selection transistors of the fifth, sixth, seventh and eighth memory cells.

15. The method of claim 12, further comprising:

forming first, second, third, fourth and fifth isolating layers;

forming the first bitline on the second isolating layer, the first bitline being arranged over the first column of memory cells;

forming the second bitline on the third isolating layer, the second bitline being arranged over the first column of memory cells;

forming the third bitline on the fifth isolating layer, the third bitline being arranged over the first column of memory cells; and

forming the fourth bitline on the fifth isolating layer, the fourth bitline being arranged over the second column of memory cells.

16. A non-volatile memory, comprising:

a first column of memory cells, the first column including first and second memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the first and second memory cells having respective gate terminals coupled to one another;

a second column of memory cells, the second column including third and fourth memory cells, the third memory cell being adjacent to the first memory cell, the fourth memory cell being adjacent to the second memory cell, the third and fourth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the third and fourth memory cells having respective gate terminals coupled to one another;

a first bitline coupled to a conduction terminal of the floating gate transistor of the first memory cell;

a second bitline coupled to a conduction terminal of the floating gate transistors of the second memory cell;

a third bitline coupled to a conduction terminal of the floating gate transistor of the third memory cell; and

a fourth bitline coupled to a conduction terminal of the floating gate transistor of the fourth memory cell, the first, second, third, and fourth bitlines being different from one another.

17. The non-volatile memory of claim 16 wherein the first, second and third bitlines are arranged over the first column of memory cells, and the fourth bitline is arranged over the second column of memory cells.

18. The non-volatile memory of claim 17, comprising:

fifth and sixth memory cells arranged in the first column, the fifth and sixth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the fifth and sixth memory cells having respective gate terminals coupled to one another;

seventh and eighth memory cells arranged in the second column, the seventh memory cell being adjacent to the fifth memory cell, the eighth memory cell being adjacent to the sixth memory cell, the seventh and eighth memory cells each including a respective selection transistor and a respective floating gate transistor, the selection transistors of the seventh and eighth memory cells having respective gate terminals coupled to one another,

wherein the first bitline is coupled to a conduction terminal of the floating gate transistor of the sixth memory cell, the second bitline is coupled to a conduction terminal of the floating gate transistor of the fifth memory cell, the third bitline is coupled to a conduction terminal of the floating gate transistor of the eighth memory cell and the fourth bitline is coupled to a conduction terminal of the floating gate transistor of the seventh memory cell.

19. The non-volatile memory of claim 18, comprising:

a first gate control line coupled to respective control gates of the floating gate transistors of the first and third memory cells;

a second gate control line coupled to respective control gates of the floating gate transistors of the second and fourth memory cells;

a third gate control line coupled to respective control gates of the floating gate transistors of the fifth and seventh memory cells; and

a fourth gate control line coupled to respective control gates of the floating gate transistors of the sixth and eighth memory cells.

20. The non-volatile memory of claim 18, comprising:

an electrically isolating layer positioned between the memory cells and the first through fourth bitlines;

a first conductive path coupling the first bitline to the conduction terminals of the floating gate transistors of the first and sixth memory cells, the first conductive path being routed through at least a portion of the electrically isolating layer;

a second conductive path coupling the second bitline to the conduction terminals of the floating gate transistors of the second and fifth memory cells, the second conductive path being routed through at least a portion of the electrically isolating layer;

a third conductive path coupling the third bitline to the conduction terminals of the floating gate transistors of the third and eighth memory cells, the third conductive path being routed through at least a portion of the electrically isolating layer; and

a fourth conductive path coupling the fourth bitline to the conduction terminals of the floating gate transistors of the fourth and seventh memory cells, the fourth conductive path being routed through at least a portion of the electrically isolating layer.