Setting a default read signal based on error correction

• US 9,941,022 B2
• Filed: 01/25/2017
• Issued: 04/10/2018
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ratnam, Sampath K., Yanamanamanda, Satish K.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US15/414,953
• Publication Number:
  US 20170132076A1
• Time in Patent Office: 440 Days
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections.

Claims

1. A method, comprising:

reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals as part of a test operation during idle time of a memory apparatus;

error correcting the lower page data read with the plurality of lower page discrete read signals;

setting one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction;

reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals as part of a test operation during idle time of a memory apparatus;

error correcting the upper page data read with the plurality of upper page discrete read signals; and

setting one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction.

2. The method of claim 1, wherein the upper page data comprises first upper page data, wherein the upper page discrete read signals comprises first upper page discrete read signals, and wherein the method includes:

reading second upper page data from the group of memory cells with each of a plurality of second upper page discrete read signals;

error correcting second upper page data read with the plurality of second upper page discrete read signals; and

setting one of the plurality of second upper page discrete read signals as a default second upper page read signal for the group of memory cells based at least in part on the error correction.

3. The method of claim 1, wherein the method includes:

reading middle page data from the group of memory cells with each of a plurality of middle page discrete read signals;

error correcting the middle page data read with the plurality of middle page discrete read signals; and

setting one of the plurality of middle page discrete read signals as a default middle page read signal for the group of memory cells based at least in part on the error correction.

4. The method of claim 1, wherein setting one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells comprises setting as the default lower page read signal one of the plurality of lower page discrete read signals that results in a fewest number of errors based at least in part on the error correction.

5. The method of claim 1, wherein setting one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells comprises setting as the default upper page read signal one of the plurality of upper page discrete read signals that results in a fewest number of errors based at least in part on the error correction.

6. The method of claim 1, further comprising error correcting the lower page of data and error correcting the upper page data as part of a test operation during idle time of a memory apparatus.

7. The method of claim 1, further comprising:

setting one of the plurality of lower page discrete signals as the default lower page read signal as part of a test operation during idle time of a memory apparatus; and

setting one of the plurality of upper page discrete read signals as the default upper page read signal as part of the test operation during idle time of the memory apparatus.

8. The method of claim 1, wherein error correcting the lower page of data further comprises error correcting at least one codeword of the lower page of data as read with at least one of the plurality of lower page discrete read signals.

9. The method of claim 1, wherein error correcting the upper page of data further comprises error correcting at least one codeword of the upper page of data as read with at least one of the plurality of upper page discrete read signals.

10. A method, comprising:

reading lower page data from a group of memory cells with a plurality of lower page discrete read signals;

counting a number of errors corrected for the lower page data read with each of the plurality of lower page discrete read signals;

comparing the number of errors corrected for each of the plurality of lower page discrete read signals;

setting one of the plurality of lower page discrete read signals as a default lower page read signal based, at least in part, on the comparison of the number of errors corrected for each of the plurality of lower page discrete read signals;

reading upper page data from the group of memory cells with a plurality of upper page discrete read signals;

counting a number of errors corrected for the upper page data read with each of the plurality of upper page discrete read signals;

comparing the number of errors corrected for each of the plurality of upper page discrete read signals; and

setting one of the plurality of upper page discrete read signals as a default upper page read signal based, at least in part, on the comparison of the number of errors corrected for each of the plurality of upper page discrete read signals.

11. The method of claim 10, wherein counting the number of errors corrected for the lower page data read comprises counting the number of errors corrected for the lower page data read with each of the plurality of lower page discrete read signals that do not return an uncorrectable error.

12. The method of claim 10, wherein counting the number of errors corrected for the upper page data read comprises counting the number of errors corrected for the upper page data read with each of the plurality of upper page discrete read signals that do not return an uncorrectable error.

13. The method of claim 10, wherein reading the lower page data comprises reading lower page user data, and wherein reading the upper page data comprises reading upper page user data.

14. The method of claim 10, wherein:

counting the number of errors corrected for the lower page data comprises counting the number of errors corrected for the lower page data during error correction after each reading of the group of memory cells with each of the plurality of lower page discrete read signals, and

counting the number of errors corrected for the upper page data comprises counting the number of errors corrected for the upper page data during error correction after each reading of the group of memory cells with each of the plurality of upper page discrete read signals.

15. A memory apparatus, comprising:

a memory including memory cells; and

a controller coupled to the memory and configured to;

read lower page data from a group of memory cells with each of a plurality of lower page discrete read signals as part of a test operation during idle time of the memory apparatus;

error correct the lower page data read with the plurality of lower page discrete read signals;

set one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least on part on the error correction;

read upper page data from the group of memory cells with each of a plurality of upper page discrete read signals as part of a test operation during idle time of the memory apparatus;

error correct the upper page data read with the plurality of upper page discrete read signals; and

set one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least on part on the error correction.

16. The apparatus of claim 15, wherein the controller is further configured to:

count a number of errors corrected as part of error correction for at least one codeword of the lower page data; and

count a number of errors corrected as part of error correction for at least one codeword of the upper page data.

17. The apparatus of claim 15, wherein the controller is further configured to:

error correct all codewords of the lower page data; and

error correct all codewords of the upper page data.

18. The apparatus of claim 15, wherein respective lower page discrete read signals among the plurality of lower page discrete read signals have different magnitudes, and wherein respective upper page discrete read signals among the plurality of upper page discrete read signals have different magnitudes.

19. A method, comprising:

reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals;

error correcting the lower page data read with the plurality of lower page discrete read signals as part of a test operation during idle time of a memory apparatus;

setting one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction;

reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals;

error correcting the upper page data read with the plurality of upper page discrete read signals as part of a test operation during idle time of a memory apparatus; and

setting one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction.

20. A method, comprising:

reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals;

error correcting the lower page data read with the plurality of lower page discrete read signals;

setting, as part of a test operation during idle time of a memory apparatus, one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction;

reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals;

error correcting the upper page data read with the plurality of upper page discrete read signals; and

setting, as part of a test operation during idle time of a memory apparatus, one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction.

21. A memory apparatus, comprising:

a memory including memory cells; and

a controller coupled to the memory and configured to;

read lower page data from a group of memory cells with each of a plurality of lower page discrete read signals;

error correct the lower page data read with the plurality of lower page discrete read signals;

count a number of errors corrected as part of error correction for at least one codeword of lower page data;

set one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least on part on the error correction;

read upper page data from the group of memory cells with each of a plurality of upper page discrete read signals;

error correct the upper page data read with the plurality of upper page discrete read signals;

count a number of errors corrected as part of error correction for at least one codeword of upper page data; and

set one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least on part on the error correction.