Setting a default read signal based on error correction
First Claim
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1. A method, comprising:
- reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals as part of a test operation during idle time of a memory apparatus;
error correcting the lower page data read with the plurality of lower page discrete read signals;
setting one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction;
reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals as part of a test operation during idle time of a memory apparatus;
error correcting the upper page data read with the plurality of upper page discrete read signals; and
setting one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction.
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Abstract
A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections.
31 Citations
21 Claims
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1. A method, comprising:
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reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals as part of a test operation during idle time of a memory apparatus; error correcting the lower page data read with the plurality of lower page discrete read signals; setting one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction; reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals as part of a test operation during idle time of a memory apparatus; error correcting the upper page data read with the plurality of upper page discrete read signals; and setting one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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reading lower page data from a group of memory cells with a plurality of lower page discrete read signals; counting a number of errors corrected for the lower page data read with each of the plurality of lower page discrete read signals; comparing the number of errors corrected for each of the plurality of lower page discrete read signals; setting one of the plurality of lower page discrete read signals as a default lower page read signal based, at least in part, on the comparison of the number of errors corrected for each of the plurality of lower page discrete read signals; reading upper page data from the group of memory cells with a plurality of upper page discrete read signals; counting a number of errors corrected for the upper page data read with each of the plurality of upper page discrete read signals; comparing the number of errors corrected for each of the plurality of upper page discrete read signals; and setting one of the plurality of upper page discrete read signals as a default upper page read signal based, at least in part, on the comparison of the number of errors corrected for each of the plurality of upper page discrete read signals. - View Dependent Claims (11, 12, 13, 14)
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15. A memory apparatus, comprising:
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a memory including memory cells; and a controller coupled to the memory and configured to; read lower page data from a group of memory cells with each of a plurality of lower page discrete read signals as part of a test operation during idle time of the memory apparatus; error correct the lower page data read with the plurality of lower page discrete read signals; set one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least on part on the error correction; read upper page data from the group of memory cells with each of a plurality of upper page discrete read signals as part of a test operation during idle time of the memory apparatus; error correct the upper page data read with the plurality of upper page discrete read signals; and set one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least on part on the error correction. - View Dependent Claims (16, 17, 18)
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19. A method, comprising:
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reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals; error correcting the lower page data read with the plurality of lower page discrete read signals as part of a test operation during idle time of a memory apparatus; setting one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction; reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals; error correcting the upper page data read with the plurality of upper page discrete read signals as part of a test operation during idle time of a memory apparatus; and setting one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction.
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20. A method, comprising:
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reading lower page data from a group of memory cells with each of a plurality of lower page discrete read signals; error correcting the lower page data read with the plurality of lower page discrete read signals; setting, as part of a test operation during idle time of a memory apparatus, one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least in part on the error correction; reading upper page data from the group of memory cells with each of a plurality of upper page discrete read signals; error correcting the upper page data read with the plurality of upper page discrete read signals; and setting, as part of a test operation during idle time of a memory apparatus, one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least in part on the error correction.
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21. A memory apparatus, comprising:
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a memory including memory cells; and a controller coupled to the memory and configured to; read lower page data from a group of memory cells with each of a plurality of lower page discrete read signals; error correct the lower page data read with the plurality of lower page discrete read signals; count a number of errors corrected as part of error correction for at least one codeword of lower page data; set one of the plurality of lower page discrete read signals as a default lower page read signal for the group of memory cells based at least on part on the error correction; read upper page data from the group of memory cells with each of a plurality of upper page discrete read signals; error correct the upper page data read with the plurality of upper page discrete read signals; count a number of errors corrected as part of error correction for at least one codeword of upper page data; and set one of the plurality of upper page discrete read signals as a default upper page read signal for the group of memory cells based at least on part on the error correction.
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Specification