Uniform dielectric recess depth during fin reveal

• US 9,941,134 B2
• Filed: 05/01/2017
• Issued: 04/10/2018
• Est. Priority Date: 10/30/2015
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Briggs, Benjamin D., Clevenger, Lawrence A., Rizzolo, Michael, Strane, Jay W.
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US15/583,638
• Publication Number:
  US 20170236717A1
• Time in Patent Office: 344 Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31056 the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Claims

1. A method for providing a uniform recess depth between different fin gap sizes, comprising:

depositing a first dielectric material over and between fins on a substrate, the first dielectric material forming trenches corresponding to wider gaps between the fins;

depositing a second dielectric material to fill in the trenches formed in the first dielectric material, the second dielectric material having a higher etch resistance than the first dielectric material;

planarizing the second dielectric material and a portion of the first dielectric material above the fins such that the second dielectric material remains only in the trenches to form plugs;

etching the first dielectric material and the plugs such that the first dielectric material is recessed into narrow gaps and the etching of the first dielectric material in the wider gaps is delayed by the plugs in the wider gaps until the plugs are removed; and

continuing etching of the first dielectric material such that a recess depth of the wider gaps catches up to the recess depth of the narrow gaps until a target depth is concurrently achieved for the first dielectric material in the narrow gaps and the wider gaps.

2. The method as recited in claim 1, wherein etching the first dielectric material and the plugs includes performing a reactive ion etch.

3. The method as recited in claim 1, wherein the first dielectric material includes an oxide and the second dielectric material includes a nitride.

4. The method as recited in claim 1, wherein the fins are etched from the substrate.

5. The method as recited in claim 1, wherein continuing etching includes reactive ion etching with an etch lag wherein the narrow gaps lag behind the wider gaps.

6. The method as recited in claim 1, wherein the fins include one or more of Si, SiGe, III-V materials or combinations thereof.

7. The method as recited in claim 1, wherein the fins include a liner, and the method further comprises recessing the liner to the target depth.

8. The method as recited in claim 1, wherein planarizing includes performing a process selected from the group consisting of a reactive ion etch and a chemical mechanical polish.

9. A method for providing a uniform recess depth between different fin gap sizes, comprising:

depositing a second dielectric material to fill in trenches formed in a first dielectric material in narrow gaps and wider gaps formed by fins on a substrate, the second dielectric material having a higher etch resistance than the first dielectric material;

planarizing the second dielectric material and a portion of the first dielectric material above the fins such that the second dielectric material remains only in the trenches to form plugs;

etching the first dielectric material and the plugs, until the plugs are removed, such that the first dielectric material is recessed into the narrow gaps; and

continuing etching of the first dielectric material until a target depth of the first dielectric material is concurrently achieved in the narrow gaps and the wider gaps.

10. The method as recited in claim 9, wherein etching the first dielectric material and the plugs includes performing a reactive ion etch.

11. The method as recited in claim 9;

wherein the first dielectric material includes an oxide and the second dielectric material includes a nitride.

12. The method as recited in claim 9, wherein the fins are etched from the substrate.

13. The method as recited in claim 9, wherein continuing etching includes reactive ion etching with an etch lag wherein the narrow gaps lag behind the wider gaps.

14. The method as recited in claim 9, wherein the fins include one or more of Si, SiGe, III-V materials or combinations thereof.

15. The method as recited in claim 9, wherein the fins include a liner, and the method further comprises recessing the liner to the target depth.

16. The method as recited in claim 9, wherein planarizing includes performing a process selected from the group consisting of a reactive ion etch and a chemical mechanical polish.