Three-dimensional non-volatile memory device

• US 9,941,291 B2
• Filed: 10/09/2015
• Issued: 04/10/2018
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Ki Hong, Pyi, Seung Ho, Kim, Il Do
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): SWAN, GARDNER W.S
• Application Number:
  US14/879,790
• Publication Number:
  US 20160035732A1
• Time in Patent Office: 914 Days
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

alternately forming at least one first material layer and second material layers over a substrate;

forming a first slit through the first and second material layers;

forming a first insulating layer in the first slit;

alternately forming third material layers and fourth material layers over a resultant structure including the first insulating layer;

forming a second slit and a third slit passing through the first to fourth material layers, wherein the first slit is disposed between the second slit and the third slit;

forming recessed regions by removing the first and third material layers exposed through the second and third slits; and

forming conductive layers in the recessed regions, the conductive layers including upper conductive layers above the first slit, wherein the upper conductive layers completely cover a central portion of the first slit and the first insulating layer.

2. The method of claim 1, wherein the second slit is located in a cell region, and the third slit is located in a contact region.

3. The method of claim 1, wherein each of the first and second material layers is divided into a plurality of patterns by the first to third slits.

4. The method of claim 1, wherein each of the third and fourth material layers has a shape of a plate including openings formed by the second and third slits.

5. The method of claim 1, further comprising:

forming a first source layer on the substrate before the alternately forming of the first and second material layers;

forming a trench by etching the first source layer;

forming a sacrificial layer in the trench;

forming channel holes through the first material layers and the second material layers, wherein the channel holes are connected with the trench;

removing the sacrificial layer exposed on bottom surfaces of the channel holes;

forming a semiconductor layer in the trench and the channel holes;

forming a fourth slit through the trench between the channel holes;

forming a second source layer by doping the semiconductor layer formed in the trench with impurities through the fourth slit; and

forming a third source layer in the second source layer and a lower portion of the fourth slit, wherein the third source layer is coupled to the first source layer.

6. The method of claim 1, further comprising:

forming a buffer layer on the substrate before the alternately forming of the first and second material layers;

forming a trench by etching the buffer layer;

forming a sacrificial layer in the trench;

forming channel holes through the first material layers and the second material layers, wherein the channel holes are connected with the trench;

removing the sacrificial layer exposed on bottom surfaces of the channel holes;

forming a semiconductor layer in the trench and the channel holes;

forming a fourth slit between the channel holes, wherein the fourth slit is connected with the trench;

forming a first source layer by doping the semiconductor layer formed in the trench with impurities through the fourth slit; and

forming a second source layer in the first source layer.

7. The method of claim 6, further comprising:

forming an etch stop conductive layer on the substrate before the forming of the buffer layer.

8. The method of claim 1, further comprising:

forming channel holes through the first to fourth material layers; and

forming a semiconductor layer in each of the channel holes,

wherein the first to third slits are spaced from the channel holes.