Array substrate, display panel and display device
First Claim
1. An array substrate, comprising:
- a substrate;
a plurality of gate lines located on the substrate;
a plurality of data lines located on the substrate, intersecting and insulated from the plurality of gate lines, wherein the plurality of gate lines and the plurality of data lines defined a plurality of sub-pixel areas;
wherein the plurality of sub-pixel areas each comprises;
a thin-film transistor;
a pixel electrode; and
a barrier metal electrode;
wherein the thin-film transistor comprises a source electrode, a drain electrode and a gate electrode, wherein the source electrode is connected with one of the plurality of data lines, the drain electrode is connected with the pixel electrode, and the gate electrode is connected with one of the plurality of gate lines; and
wherein an orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, and an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
The present application provides an array substrate, a display panel and a display device. The array substrate includes: a substrate; gate lines and data lines located on the substrate, intersecting and insulated from each other, which define a plurality of sub-pixel areas; the sub-pixel areas each comprises: a thin-film transistor; a pixel electrode, a barrier metal electrode. An orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate.
-
Citations
17 Claims
-
1. An array substrate, comprising:
-
a substrate; a plurality of gate lines located on the substrate; a plurality of data lines located on the substrate, intersecting and insulated from the plurality of gate lines, wherein the plurality of gate lines and the plurality of data lines defined a plurality of sub-pixel areas; wherein the plurality of sub-pixel areas each comprises; a thin-film transistor; a pixel electrode; and a barrier metal electrode; wherein the thin-film transistor comprises a source electrode, a drain electrode and a gate electrode, wherein the source electrode is connected with one of the plurality of data lines, the drain electrode is connected with the pixel electrode, and the gate electrode is connected with one of the plurality of gate lines; and wherein an orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, and an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A display panel, comprising an array substrate, wherein the array substrate comprises:
-
a substrate; a plurality of gate lines located on the substrate; a plurality of data lines located on the substrate; a plurality of sub-pixel areas defined by insulated intersecting of the plurality of gate lines and the plurality of data lines; a thin-film transistor arranged corresponding to each of the plurality of sub-pixel areas; a pixel electrode arranged corresponding to each of the plurality of sub-pixel areas; and a barrier metal electrode arranged corresponding to each of the plurality of sub-pixel areas, wherein the thin-film transistor comprises a source electrode, a drain electrode and a gate electrode, the source electrode is connected with one of the plurality of data lines, the drain electrode is connected with the pixel electrode, and the gate electrode is connected with one of the plurality of gate lines;
an orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, and wherein an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate.
-
-
17. A display device, comprising a display panel, wherein the display panel comprises an array substrate, and the array substrate comprises:
-
a substrate; a plurality of gate lines located on the substrate; and a plurality of data lines located on the substrate, intersecting and insulated from the plurality of gate lines, wherein the plurality of gate lines and the plurality of data lines defined a plurality of sub-pixel areas; wherein the plurality of sub-pixel areas each comprises; a thin-film transistor; a pixel electrode; and a barrier metal electrode; wherein the thin-film transistor comprises a source electrode, a drain electrode and a gate electrode, the source electrode is connected with one of the plurality of data lines, the drain electrode is connected with the pixel electrode, and the gate electrode is connected with one of the plurality of gate lines; and wherein an orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, and wherein an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate.
-
Specification