Memory device, semiconductor device, and electronic device

• US 9,941,304 B2
• Filed: 08/01/2016
• Issued: 04/10/2018
• Est. Priority Date: 12/25/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US15/224,726
• Publication Number:
  US 20170033128A1
• Time in Patent Office: 617 Days
• Field of Search: 438238, 438241, 438258, 438266, 257277, 257298, 257300, 257368, 257E27001, 257E27081, 257E27009, 257E27014, 326 95, 326 98, 326119, 326120
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

A memory device does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Claims

1. A memory element comprising:

a first logic element and a second logic element, wherein an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and an output terminal of the second logic element is electrically connected to an input terminal of the first logic element;

a first transistor comprising an oxide semiconductor film including a channel formation region; and

a first capacitor electrically connected to the input terminal of the first logic element and the output terminal of the second logic element through a source electrode and a drain electrode of the first transistor,

wherein at least one of the first logic element and the second logic element comprises a second transistor comprising a crystalline silicon film including a channel formation region,

wherein a first insulating film is provided over the second transistor,

wherein the first transistor is provided over the first insulating film, and

wherein the first capacitor is provided over the first insulating film.

2. The memory element according to claim 1, wherein the oxide semiconductor film comprises indium, gallium, and zinc.

3. The memory element according to claim 1, wherein the crystalline silicon film is a single crystal silicon film.

4. The memory element according to claim 1, wherein a second insulating film is provided between the first insulating film and the first transistor.

5. The memory element according to claim 1, wherein the first capacitor is provided in the same layer as the first transistor.

6. The memory element according to claim 1, comprising a third transistor, wherein the output terminal of the second logic element is electrically connected to the input terminal of the first logic element through a source electrode and a drain electrode of the third transistor.

7. The memory element according to claim 1, comprising third transistor and a second capacitor electrically connected to the output terminal of the first logic element and the input terminal of the second logic element through a source electrode and a drain electrode of the third transistor.

8. The memory element according to claim 1, wherein the first transistor comprises:

a gate electrode;

a gate insulating film over the gate electrode; and

the oxide semiconductor film over the gate insulating film.

9. The memory element according to claim 1, wherein the first transistor comprises:

the source electrode and the drain electrode;

the oxide semiconductor film over the source electrode and the drain electrode;

a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and

a gate electrode over the gate insulating film.

10. A CPU comprising:

a register comprising a memory element comprising;

a first logic element and a second logic element, wherein an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and an output terminal of the second logic element is electrically connected to an input terminal of the first logic element;

a first transistor comprising an oxide semiconductor film including a channel formation region; and

a first capacitor electrically connected to the input terminal of the first logic element and the output terminal of the second logic element through a source electrode and a drain electrode of the first transistor,

wherein at least one of the first logic element and the second logic element comprises a second transistor comprising a crystalline silicon film including a channel formation region,

wherein a first insulating film is provided over the second transistor, and

wherein the first transistor is provided over the first insulating film,

an arithmetic logic unit; and

a register controller configured to select holding operation in the register in accordance with an instruction from the arithmetic logic unit.

11. The CPU according to claim 10, wherein the oxide semiconductor film comprises indium, gallium, and zinc.

12. The CPU according to claim 10, wherein the crystalline silicon film is a single crystal silicon film.

13. The CPU according to claim 10, wherein a second insulating film is provided between the first insulating film and the first transistor.

14. The CPU according to claim 10, wherein the first capacitor is provided in the same layer as the first transistor.

15. The CPU according to claim 10,

wherein the memory element comprises a third transistor, and

wherein the output terminal of the second logic element is electrically connected to the input terminal of the first logic element through a source electrode and a drain electrode of the third transistor.

16. The CPU according to claim 10,

wherein the memory element comprises a third transistor and a second capacitor electrically connected to the output terminal of the first logic element and the input terminal of the second logic element through a source electrode and a drain electrode of the third transistor.

17. The CPU according to claim 10, wherein the first transistor comprises:

a gate electrode;

a gate insulating film over the gate electrode; and

the oxide semiconductor film over the gate insulating film.

18. The CPU according to claim 10, wherein the first transistor comprises:

the source electrode and the drain electrode;

the oxide semiconductor film over the source electrode and the drain electrode;

a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and

a gate electrode over the gate insulating film.

19. The CPU according to claim 10, wherein the first capacitor is provided over the first insulating film.