Semiconductor and optoelectronic methods and devices

• US 9,941,319 B2
• Filed: 11/09/2015
• Issued: 04/10/2018
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C.
• Primary Examiner(s): Wang, Xi
• Application Number:
  US14/936,657
• Publication Number:
  US 20160064439A1
• Time in Patent Office: 883 Days
• Field of Search: 257222, 257225, 257447, 348308, 348311, 348340, 348345, 348357
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14647 Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

Claims

1. An image sensor, comprising:

a mono-crystallized silicon layer comprising a plurality of image sensor pixels, said mono-crystallized silicon layer bonded to a carrier wafer,

wherein said mono-crystallized silicon layer bonded to said carrier wafer leaves a re-useable base wafer used to hold said mono-crystallized silicon layer;

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide,

wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels,

wherein said plurality of single crystal transistors overlay said image sensor pixels, and wherein said second mono-crystal layer is less than 2 microns thick.

2. An image sensor wafer, comprising:

a mono-crystallized silicon layer comprising a plurality of image sensor pixels, said mono-crystallized silicon layer bonded to a carrier wafer,

wherein said mono-crystallized silicon layer bonded to said carrier wafer leaves a re-useable base wafer used to hold said mono-crystallized silicon layer;

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide, wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels,

wherein said plurality of single crystal transistors overlay said image sensor pixels, and wherein said single crystal transistors form a plurality of pixel control circuits.

3. An image sensor wafer, comprising:

a mono-crystallized silicon layer comprising a plurality of image sensor pixels, said mono-crystallized silicon layer bonded to a carrier wafer,

wherein said mono-crystallized silicon layer bonded to said carrier wafer leaves a re-useable base wafer used to hold said mono-crystallized silicon layer;

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide, wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels, and wherein said plurality of single crystal transistors overlay said image sensor pixels.

4. An image sensor wafer according to claim 3,

wherein said second mono-crystal layer is less than 2 microns thick.

5. An image sensor wafer according to claim 3,

wherein said mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer.

6. An image sensor wafer according to claim 3,

wherein said mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first transistors layer and a second transistors layer.

7. An image sensor wafer according to claim 3,

wherein said mono-crystallized silicon layer is less than 6 microns thick.

8. An image sensor wafer according to claim 3,

wherein said single crystal transistors form a plurality of pixel control circuits.

9. An image sensor wafer, comprising:

a mono-crystallized silicon layer comprising a plurality of image sensor pixels, said mono-crystallized silicon layer bonded to a carrier wafer;

wherein said carrier wafer comprises a mono-crystal layer comprising a plurality of single crystal transistors,

wherein said plurality of single crystal transistors are aligned to said image sensor pixels with less than 100 nm alignment error, and

wherein said plurality of single crystal transistors overlay said image sensor pixels.

10. An image sensor wafer according to claim 9, further comprising:

an oxide layer between said mono-crystallized silicon layer and said carrier wafer.

11. An image sensor wafer according to claim 9,

wherein said mono-crystallized silicon layer is less than 2 microns thick.

12. An image sensor wafer according to claim 9,

wherein said image sensor pixels layer comprises two crystalline layers, and

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer.

13. An image sensor wafer according to claim 9,

wherein said carrier wafer comprises two crystalline layers,

wherein said two crystalline layers comprise a first transistor layer and a second transistor layer.

14. An image sensor wafer according to claim 9,

wherein said image sensor pixels layer is less than 6 microns thick.

15. An image sensor wafer according to claim 9,

wherein said mono-crystallized silicon layer bonded to said carrier wafer leaves a re-useable base wafer used to hold said mono-crystallized silicon layer.