Semiconductor memory device and structure

• US 9,941,332 B2
• Filed: 01/19/2017
• Issued: 04/10/2018
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, Wurman, Zeev
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US15/409,740
• Publication Number:
  US 20170133432A1
• Time in Patent Office: 446 Days
• CPC Class Codes: G11C 13/0021 Auxiliary circuits
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/04 : characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/167 : further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66568 : Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/023 : by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

Claims

1. A semiconductor memory, comprising:

a first memory cell comprising a first transistor;

a second memory cell comprising a second transistor; and

a memory peripherals transistor overlaying said second transistor or underneath said first transistor,

wherein said second memory cell overlays said first memory cell,

wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and

wherein said memory peripherals transistor is part of a peripherals circuit controlling said memory.

2. The semiconductor memory according to claim 1,

wherein said second transistor comprises a single crystal channel.

3. The semiconductor memory according to claim 1,

wherein said first transistor is a polysilicon transistor.

4. The semiconductor memory according to claim 1,

wherein said first transistor is a junction-less transistor.

5. The semiconductor memory according to claim 1, further comprising:

an isolation layer disposed between said memory peripherals transistor and said first transistor.

6. The semiconductor memory according to claim 1,

wherein said memory peripherals transistor comprises a single crystal channel.

7. The semiconductor memory according to claim 1,

wherein said first transistor and said memory peripherals transistor have a misalignment to each other of less than 40 nm.

8. A semiconductor memory, comprising:

a first memory cell comprising a first transistor;

a second memory cell comprising a second transistor; and

a memory peripherals transistor overlaying said second transistor or underneath said first transistor,

wherein said second memory cell overlays said first memory cell,

wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and

wherein said first transistor and said memory peripherals transistor have a misalignment to each other of less than 40 nm.

9. The semiconductor memory according to claim 8,

wherein said second transistor comprises a single crystal channel.

10. The semiconductor memory according to claim 8,

wherein said first transistor is a polysilicon transistor.

11. The semiconductor memory according to claim 8,

wherein said first transistor is a junction-less transistor.

12. The semiconductor memory according to claim 8, further comprising:

an isolation layer disposed between said memory peripherals transistor and said first transistor.

13. The semiconductor memory according to claim 8,

wherein said memory peripherals transistors comprises a single crystal channel.

14. The semiconductor memory according to claim 8,

wherein said memory peripherals transistor is part of a peripherals circuit controlling said memory.

15. A semiconductor memory, comprising:

a first memory cell comprising a first transistor;

a second memory cell comprising a second transistor; and

a memory peripherals transistor overlaying said second transistor or underneath said first transistor,

wherein said second memory cell overlays said first memory cell,

wherein said first memory cell and said second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and

wherein said memory peripherals transistor comprises a single crystal channel and is part of a peripherals circuit controlling said memory.

16. The semiconductor memory according to claim 15,

wherein said second transistors comprises a single crystal channel.

17. The semiconductor memory according to claim 15,

wherein said first transistor is a polysilicon transistor.

18. The semiconductor memory according to claim 15,

wherein said first transistor is a junction-less transistor.

19. The semiconductor memory according to claim 15, further comprising:

an isolation layer disposed between said memory peripherals transistor and said first transistor,

wherein said isolation layer comprises a via having a radius of less than 400 nm.

20. The semiconductor memory according to claim 15,

wherein said first transistor and said memory peripherals transistor have a misalignment to each other of less than 40 nm.