Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods

• US 9,941,359 B2
• Filed: 05/13/2016
• Issued: 04/10/2018
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert J., Takeuchi, Hideki
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/154,276
• Publication Number:
  US 20160336406A1
• Time in Patent Office: 697 Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of first transistors having a first operating voltage, each first transistor comprising spaced-apart first source and drain regions, a first channel between the first source and drain regions, and a first punch-through stop (PTS) layer in the semiconductor substrate, the first PTS layer being at a first depth below the first channel; and

a plurality of second transistors having a second operating voltage higher than the first operating voltage, each second transistor comprising spaced-apart second source and drain regions, a second channel between the second source and drain regions, and a second PTS layer in the semiconductor substrate, the second PTS layer being at a second depth below the second channel and being greater than the first depth, and also being above a bottom of the second source and drain regions;

the first channel comprising a first superlattice, and the second channel comprising a second superlattice;

wherein the first PTS layer is physically separated from the first channel by a first intervening semiconductor region, and the second PTS layer is physically separated from the second channel by a second intervening semiconductor region.

2. The semiconductor device of claim 1 wherein the first and second superlattices each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

3. The semiconductor device of claim 2 wherein each base semiconductor portion comprises silicon.

4. The semiconductor device of claim 2 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

5. The semiconductor device of claim 2 wherein the at least one non-semiconductor layer comprises oxygen.

6. The semiconductor device of claim 1 wherein the plurality of first transistors comprises a plurality of core transistors, and the plurality of second transistors comprises a plurality of input/output transistors.

7. The semiconductor device of claim 1 wherein the first and second PTS layers each comprises a highly doped semiconductor layer.

8. The semiconductor device of claim 1 wherein the first channel comprises an adjacent first portion of the semiconductor substrate below the first superlattice, and the second channel comprises an adjacent second portion of the semiconductor substrate below the second superlattice.

9. The semiconductor device of claim 1 wherein each of the first transistors comprises a first gate overlying the first channel, and spaced apart first source and drain regions on opposite sides of the first gate;

and wherein each of the second transistors comprises a second gate overlying the second channel, and spaced apart second source and drain regions on opposite sides of the second gate.

10. A semiconductor device comprising:

a semiconductor substrate;

a plurality of first transistors having a first operating voltage, each first transistor comprising spaced-apart first source and drain regions, a first channel between the first source and drain regions, and a first punch-through stop (PTS) layer in the semiconductor substrate, the first PTS layer being at a first depth below the first channel; and

a plurality of second transistors having a second operating voltage higher than the first operating voltage, each second transistor comprising spaced-apart second source and drain regions, a second channel between the second source and drain regions, and a second PTS layer in the semiconductor substrate, the second PTS layer being at a second depth below the second channel and being greater than the first depth, and also being above a bottom of the second source and drain regions;

the first channel comprising a first superlattice, and the second channel comprising a second superlattice;

the first and second superlattices each comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

the plurality of first transistors comprising a plurality of core transistors, and the plurality of second transistors comprising a plurality of input/output transistors;

wherein the first PTS layer is physically separated from the first channel by a first intervening semiconductor region, and the second PTS layer is physically separated from the second channel by a second intervening semiconductor region.

11. The semiconductor device of claim 10 wherein each base semiconductor portion comprises silicon.

12. The semiconductor device of claim 10 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

13. The semiconductor device of claim 10 wherein the at least one non-semiconductor layer comprises oxygen.

14. The semiconductor device of claim 10 wherein the first and second punch-through stop layers each comprises a highly doped semiconductor layer.

15. The semiconductor device of claim 10 wherein the first channel comprises an adjacent first portion of the semiconductor substrate below the first superlattice, and the second channel comprises an adjacent second portion of the semiconductor substrate below the second superlattice.

16. The semiconductor device of claim 10 wherein each of the first transistors comprises a first gate overlying the first channel, and spaced apart first source and drain regions on opposite sides of the first gate;

and wherein each of the second transistors comprises a second gate overlying the second channel, and spaced apart second source and drain regions on opposite sides of the second gate.

17. A method of making a semiconductor device comprising:

forming a plurality of first transistors having a first operating voltage, each first transistor comprising spaced-apart first source and drain regions, a first channel between the first source and drain regions, and a first punch-through stop (PTS) layer in a semiconductor substrate, the first PTS layer being at a first depth below the first channel, and the first channel comprising a first superlattice; and

forming a plurality of second transistors having a second operating voltage higher than the first operating voltage, each second transistor comprising spaced-apart second source and drain regions, a second channel between the second source and drain regions, and a second PTS layer in the semiconductor substrate, the second PTS layer being at a second depth below the second channel and being greater than the first depth and also being above a bottom of the second source and drain regions, and the second channel comprising a second superlattice;

wherein the first PTS layer is physically separated from the first channel by a first intervening semiconductor region, and the second PTS layer is physically separated from the second channel by a second intervening semiconductor region.

18. The method of claim 17 wherein the first and second superlattices each comprises a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

19. The method of claim 18 wherein each base semiconductor portion comprises silicon.

20. The method of claim 18 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

21. The method of claim 18 wherein the at least one non-semiconductor layer comprises oxygen.

22. The method of claim 17 wherein forming the plurality of first transistors comprises forming a plurality of core transistors, and forming the plurality of second transistors comprises forming a plurality of input/output transistors.

23. The method of claim 17 wherein the first and second punch-through stop layers each comprises a highly doped semiconductor layer.