Method for forming a stress-reduced field-effect semiconductor device

• US 9,941,365 B2
• Filed: 06/22/2016
• Issued: 04/10/2018
• Est. Priority Date: 03/26/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Sedlmaier, Stefan, Zundel, Markus, Hirler, Franz, Baumgartl, Johannes, Mauder, Anton, Siemieniec, Ralf, Blank, Oliver, Hutzler, Michael
• Primary Examiner(s): Gumedzoe, Peniel M
• Assistant Examiner(s): JOHNSON, CHRISTOPHER A
• Application Number:
  US15/189,152
• Publication Number:
  US 20160300914A1
• Time in Patent Office: 657 Days
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for producing a field-effect semiconductor device includes providing a semiconductor body with a first surface defining a vertical direction, defining an active area, forming a vertical trench from the first surface into the semiconductor body, forming a field dielectric layer at least on a side wall and a bottom wall of the vertical trench, depositing a conductive layer on the field dielectric layer, forming a closed cavity on the conductive layer in the vertical trench, and forming an insulated gate electrode on the closed cavity in the vertical trench.

Claims

1. A method for producing a field-effect semiconductor device, the method comprising:

providing a semiconductor body with a first surface defining a vertical direction;

defining an active area;

forming a vertical trench from the first surface into the semiconductor body;

forming a field dielectric layer at least on a side wall and a bottom wall of the vertical trench;

depositing a conductive layer on the field dielectric layer;

forming a closed cavity on the conductive layer in the vertical trench; and

forming an insulated gate electrode on the closed cavity in the vertical trench,

wherein an interface between the field dielectric layer and the surrounding semiconductor body is under tensile stress and the closed cavity is filled or unfilled so as to counteract the tensile stress.

2. The method of claim 1, wherein depositing the conductive layer comprises depositing poly-silicon.

3. The method of claim 1, wherein the conductive layer is conformally deposited.

4. The method of claim 1, wherein forming the closed cavity comprises:

filling the vertical trench with a filler material selectively etchable with respect to the conductive layer and the field dielectric layer.

5. The method of claim 1, wherein forming the closed cavity comprises:

back-etching a filler material in the vertical trench and the conductive layer.

6. The method of claim 1, wherein forming the closed cavity comprises:

back-etching the field dielectric layer.

7. The method of claim 1, wherein forming the closed cavity comprises:

depositing a further conductive layer on and comprised of the same material as the conductive layer.

8. The method of claim 1, wherein forming the closed cavity comprises:

forming an open cavity in the conductive layer.

9. The method of claim 1, wherein forming the closed cavity comprises:

forming an open cavity in a dielectric layer.

10. The method of claim 1, wherein forming the closed cavity comprises:

closing the open cavity by at least one of depositing a further conductive layer on the open cavity, depositing a BPSG-layer from the first surface and thermal oxidizing.

11. The method of claim 1, wherein the closed cavity is formed such that the cavity has a horizontal extension larger than about 20 nm and a vertical extension larger than the horizontal extension.

12. A method for producing a field-effect semiconductor device, comprising:

providing a semiconductor wafer with a first surface defining a vertical direction;

defining an active area of the field-effect semiconductor device;

forming in the active area at least one trench gate electrode and a gate dielectric region, the gate dielectric region insulating the trench gate electrode from the semiconductor wafer;

forming in the active area dielectric regions extending from the first surface vertically deeper into the semiconductor wafer than the gate dielectric region; and

forming a vertical trench extending from the first surface vertically deeper into the semiconductor wafer than the gate dielectric region to form an expansion joint,

wherein the at least one trench gate electrode and the gate dielectric region are formed in a first trench that vertically extends from the first surface into the semiconductor wafer, and

wherein the dielectric regions and the expansion joint are formed in a second trench that is laterally separated from the first trench and extends from the first surface into the semiconductor wafer.

13. The method of claim 12, further comprising:

filling the vertical trench with an elastic material.

14. The method of claim 12, further comprising:

forming a dielectric plug on the vertical trench to form a closed cavity.

15. The method of claim 12, wherein forming the dielectric regions and forming the vertical trench comprise at least one of the following common steps:

etching wide vertical trenches from the first surface into the semiconductor wafer; and

insulating side walls of the wide vertical trenches to form dielectric regions in the active area and a placeholder of the vertical trench.

16. A method for producing a field-effect semiconductor device, the method comprising:

providing a semiconductor body with a first surface defining a vertical direction;

defining an active area;

forming a vertical trench from the first surface into the semiconductor body;

forming a field dielectric layer at least on a side wall and a bottom wall of the vertical trench;

depositing a conductive layer on the field dielectric layer;

forming a closed cavity on the conductive layer in the vertical trench; and

forming an insulated gate electrode on the closed cavity in the vertical trench,

wherein forming the closed cavity comprises;

isotropic back-etching a filler material in the vertical trench selectively with respect to the conductive layer and the field dielectric layer.