Method of fabricating a vertical MOS transistor

• US 9,941,390 B2
• Filed: 11/19/2015
• Issued: 04/10/2018
• Est. Priority Date: 01/08/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Boivin, Philippe
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Gauthier, Steven B
• Application Number:
  US14/946,408
• Publication Number:
  US 20160079391A1
• Time in Patent Office: 873 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.

Claims

1. A method, comprising:

providing a semiconductor substrate having a semiconductor surface;

forming a vertical MOS transistor over the semiconductor surface of the semiconductor substrate, the forming of the vertical MOS transistor structure including;

forming, above the semiconductor surface, a dielectric layer and a conductive layer in the dielectric layer;

etching a hole through the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface;

forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the portion of the semiconductor surface;

forming an etch-protection semiconductor sidewall on a lateral edge of the hole, the etch-protection semiconductor sidewall covering the gate dielectric and an outer region of the bottom dielectric, leaving an inner region of the bottom dielectric exposed;

doping the etch-protection semiconductor sidewall with dopants of a second conductivity type;

etching the exposed inner region of the bottom dielectric until the semiconductor surface is reached; and

depositing a semiconductor material in the hole.

2. The method according to claim 1 further comprising forming, in the semiconductor surface, a doped region including dopants of a first conductivity type.

3. The method according to claim 2 further comprising forming a conduction terminal of the transistor by diffusing dopants from the doped region into the semiconductor material in the hole.

4. The method according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

5. The method according to claim 1, wherein forming the etch-protection semiconductor sidewall on the lateral edge of the hole comprises depositing through chemical vapor deposition a layer of polysilicon.

6. The method according to claim 1 further comprising:

implanting dopants into a top surface of the semiconductor material; and

diffusing dopants in the top surface of the semiconductor material into the hole to form a conduction terminal of the transistor.

7. The method according to claim 1 further comprising, after forming the gate dielectric:

forming a charge storage layer covering the gate dielectric; and

forming a tunnel dielectric layer covering the charge storage layer.

14. The method according to claim 1 further comprising:

after forming the gate dielectric,

forming a charge storage layer covering the gate dielectric;

forming a tunnel dielectric layer covering the charge storage layer; and

wherein forming the protection sidewall on the sidewall surface of the hole includes forming the protection sidewall on the tunnel dielectric layer, the protection sidewall covering the tunnel dielectric layer and the charge storage layer, tunnel dielectric layer, and protection sidewall covering an outer portion of the bottom dielectric while leaving an inner portion of the bottom dielectric exposed.

8. A method, comprising:

providing a semiconductor substrate having a surface, the semiconductor substrate having a first conductivity type;

forming a dielectric layer above the surface of the semiconductor substrate;

forming a conductive layer in the dielectric layer;

forming a hole through the conductive layer, the hole exposing through a sidewall surface of the hole an inner lateral edge of the conductive layer, and the hole exposing through a bottom surface a portion of the surface of the semiconductor substrate;

forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the exposed portion of the surface of the semiconductor substrate;

forming a protection sidewall on the sidewall surface of the hole, the protection sidewall covering the gate dielectric and the protection sidewall also covering an outer portion of the bottom dielectric, the protection sidewall leaving an inner portion of the bottom dielectric exposed;

removing the exposed inner portion of the bottom dielectric to expose the portion of the surface of the semiconductor substrate;

forming a semiconductor material in the hole, the semiconductor material having the first conductivity type;

forming a doped region including dopants of a second conductivity type in the semiconductor substrate; and

diffusing dopants from the doped region into the semiconductor material in the hole to form through this diffusion of dopants a first conduction terminal of the transistor.

9. The method of claim 8, wherein forming the hole through the conductive layer comprises etching the hole through the conductive layer.

10. The method of claim 8, wherein removing the exposed inner portion of the bottom dielectric comprises etching the exposed inner portion of the bottom dielectric.

11. The method of claim 8, wherein forming the semiconductor material in the hole comprises depositing doped polycrystalline silicon in the hole.

12. The method of claim 8, wherein forming the protection sidewall on the sidewall surface of the hole comprises:

forming a semiconductor protection sidewall on the sidewall surface of the hole; and

doping the semiconductor protection sidewall with dopants of the first conductivity type.

13. The method according to claim 12, further comprising:

implanting dopants of the second conductivity type into an upper surface of the semiconductor material; and

diffusing the dopants implanted into the upper surface of the semiconductor material into the hole to form a second conduction terminal of the transistor.

15. A method of forming a vertical MOS transistor, comprising:

forming a doped region including dopants of a first conductivity type in a semiconductor substrate;

forming a dielectric layer above a surface of the semiconductor substrate;

forming a conductive layer in the dielectric layer;

forming a hole through the conductive layer, the hole exposing through a sidewall surface of the hole an inner lateral edge of the conductive layer, and the hole exposing through a bottom surface of the hole a portion of the surface of the semiconductor substrate;

forming a gate dielectric on the inner lateral edge of the conductive layer and a bottom dielectric on the exposed portion of the surface of the semiconductor substrate;

forming a protection sidewall on the sidewall surface of the hole, the protection sidewall covering the gate dielectric and the protection sidewall also covering an outer portion of the bottom dielectric, the protection sidewall leaving an inner portion of the bottom dielectric exposed;

removing the exposed inner portion of the bottom dielectric to expose the portion of the surface of the semiconductor substrate;

forming a semiconductor material in the hole;

diffusing dopants from the doped region into the semiconductor material in the hole to form, through this diffusion of dopants from the doped region, a first conduction terminal;

implanting dopants of the first conductivity type into an upper surface of the semiconductor material; and

diffusing dopants in the upper surface of the semiconductor material into the hole to form, through this diffusion of dopants from the upper surface of the semiconductor material, a second conduction terminal, wherein a portion of the semiconductor material between the first and second conduction terminals forms a channel region of the vertical MOS transistor.

16. The method of forming a vertical MOS transistor of claim 15, wherein forming the protection sidewall on the sidewall surface of the hole comprises:

forming a semiconductor protection sidewall on the sidewall surface of the hole; and

doping the semiconductor protection sidewall with dopants of a second conductivity type.

17. The method of forming a vertical MOS transistor of claim 15 further comprising:

after forming the gate dielectric,

forming a charge storage layer covering the gate dielectric;

forming a tunnel dielectric layer covering the charge storage layer; and

wherein forming the protection sidewall on the sidewall surface of the hole includes forming the protection sidewall on the tunnel dielectric layer, the protection sidewall covering the tunnel dielectric layer and the charge storage layer, tunnel dielectric layer, and protection sidewall covering an outer portion of the bottom dielectric while leaving an inner portion of the bottom dielectric exposed.