High frequency multi-level inverter

• US 9,941,813 B2
• Filed: 03/14/2013
• Issued: 04/10/2018
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Solaredge Technologies Incorporated
• Original Assignee: Solaredge Technologies Incorporated
• Inventors: Yoscovich, Ilan
• Primary Examiner(s): Zhang, Jue
• Assistant Examiner(s): Jackson, Lakaisha
• Application Number:
  US13/826,556
• Publication Number:
  US 20140268965A1
• Time in Patent Office: 1,853 Days
• Field of Search: 363 17, 363 65, 363 71, 363127, 363131, 363132
• CPC Class Codes: H02M 1/0043 Converters switched with a phase shift, i.e. interleaved non-isolated DC/DC converters H02M3/1586
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 7/42 Conversion of dc power input into ac power output without possibility of reversal
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4837 Flying capacitor converters
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A multi-level inverter having at least two banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Claims

1. A method comprising:

generating a periodic waveform having a first frequency by switching, at different times and at a second frequency, each of a plurality of transistors connected in series in a first bank of a multi-level inverter, wherein the second frequency is greater than the first frequency.

2. The method of claim 1, further comprising:

turning on all of the plurality of transistors at different times within each period of the second frequency.

3. The method of claim 2, wherein the switching of each transistor of the plurality of transistors is shifted from the switching of a previous transistor of the plurality of transistors based on a duration of the period of the second frequency divided by the number of transistors of the plurality of transistors.

4. The method of claim 1, wherein the second frequency is above 16 kHz, and wherein less than a maximum of 120V is maintained across terminals of each of the plurality of transistors.

5. The method of claim 1, wherein the multi-level inverter comprises four banks of transistors, wherein the first bank is connected in series with a second bank, a third bank is connected in series with a fourth bank, and the first bank and the second bank are parallel to the third bank and the fourth bank, and

wherein the method further comprises:

providing a first control signal to switch a transistor of the first bank and a transistor of the fourth bank; and

providing an inverted first control signal comprising an inverted version of the first control signal to switch a transistor of the second bank and a transistor of the third bank.

6. The method of claim 1, further comprising:

switching the plurality of transistors with respective duty cycle ratios that change, for each period of the second frequency, according to the periodic waveform.

7. The method of claim 6, wherein the periodic waveform is a rectified sine-wave.

8. An apparatus comprising:

a multi-level inverter comprising;

at least two banks, wherein a first bank and a second bank are connected in series between an input voltage and a reference voltage and each of the first bank and the second bank comprises a plurality of transistors connected in series; and

a plurality of capacitors, each of the capacitors connected between two adjacent transistors of the first bank and two adjacent transistors of the second bank; and

a controller configured to cause the multi-level inverter to generate a periodic waveform having a first frequency by;

controlling each transistor of the plurality of transistors of the first bank to switch at different times and at a second frequency, and

controlling each transistor of the plurality of transistors of the second bank to switch at different times and at the second frequency, wherein the second frequency is greater than the first frequency.

9. The apparatus of claim 8, wherein the first bank connected in series with the second bank form a second frequency stage,

wherein a third bank and a fourth bank parallel to the third bank form a first frequency stage, wherein the third bank and the fourth bank are coupled in parallel to the second bank through an inductor, and

wherein the controller is configured to:

switch the plurality of transistors of the first bank with a plurality of first control signals,

switch the plurality of transistors of the second bank with a plurality of inverted first control signals, and

switch a plurality of transistors of the third bank and a plurality of transistors of the fourth banks.

10. The apparatus of claim 9, wherein the controller is configured to switch each of the plurality of transistors of the first bank and the plurality of transistors of the second bank at a cycle frequency of about 200 kHz and to switch each of the plurality of transistors of the third bank and the plurality of transistors of the fourth bank at a cycle frequency of about 50 Hz.

11. The apparatus of claim 9, wherein the controller is configured to turn on all of the plurality of transistors of the first bank at different times within each period of the second frequency.

12. The apparatus of claim 11, wherein the controller is configured to turn on each transistor of the plurality of transistors of the first bank at a delay from turning on a previous transistor of the plurality of transistors of the first bank based on a duration of the period of the second frequency divided by the number of transistors of the plurality of transistors.

13. The apparatus of claim 8, wherein the multi-level inverter comprises a third bank and a fourth bank connected in series to each other, wherein the third bank and the fourth bank are parallel to the first bank and the second bank.

14. The apparatus of claim 13, wherein the controller is configured to send a first control signal to a first transistor of the first bank and a first transistor of the fourth bank, and an inverted version of the first control signal to a first transistor of the second bank and a first transistor of the third bank.

15. The apparatus of claim 8, wherein the controller is configured to switch the plurality of transistors of the first bank and the plurality of transistors of the second bank with respective duty cycle ratios that change, for each period of the second frequency, according to the periodic waveform.

16. The apparatus of claim 15, wherein the periodic waveform is a rectified sine-wave.

17. A multi-level inverter, comprising:

a first bank of a plurality of MOSFET transistors connected in series;

a second bank of a plurality of MOSFET transistors connected in series, wherein the first bank is connected in series to the second bank and the first bank and the second banks each comprise a first number of transistors, and wherein the first bank and the second bank are connected in series between an input voltage and a reference voltage;

a third bank of a plurality of MOSFET transistors connected in series between an inductor and the reference voltage; and

a fourth bank of a plurality of MOSFET transistors connected in series between the inductor and the reference voltage and in parallel to the third bank, wherein the inductor is further connected to a node between the first bank and the second bank; and

a plurality of capacitors, wherein each capacitor is connected between two adjacent transistors of the first bank and two adjacent transistors of the second bank.

18. The multi-level inverter of claim 17, wherein the MOSFET transistors operate at 120V or less.

19. The multi-level inverter of claim 17,

wherein the first bank and the second bank are configured to operate at a first frequency, and

wherein the third bank and the fourth bank are configured to operate at a second frequency lower than the first frequency.

20. The multi-level inverter of claim 17, wherein an output between the first bank and the second bank outputs a rectified sine-wave and wherein the third bank and the fourth bank are configured to invert portions of the rectified sine-wave.