AC coupled level shifting circuit

• US 9,941,884 B2
• Filed: 08/31/2016
• Issued: 04/10/2018
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Block, Inc. (f/k/a Square, Inc.)
• Original Assignee: Square Inc (Block, Inc. (f/k/a Square, Inc.))
• Inventors: Rezayee, Afshin, Shivnaraine, Ravi, Rousson, Alain, Yang, Yue, Julavittayanukool, Kajornsak
• Primary Examiner(s): CHEN, PATRICK C
• Application Number:
  US15/253,769
• Publication Number:
  US 20180062656A1
• Time in Patent Office: 587 Days
• Field of Search: 327333
• CPC Class Codes: G06K 7/084 sensing magnetic material by relative movement detecting flux changes without altering its magnetised state
• CPC Class Codes: G06Q 20/08 Payment architectures
• CPC Class Codes: G06Q 20/34 using cards, e.g. integrated circuit [IC] cards or magnetic cards
• CPC Class Codes: G07F 7/0873 Details of the card reader
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifting circuit can be used to adjust the level of the input signal to a desired output level while maintaining the duty cycle of the input signal. The level shifting circuit can include a capacitor to AC couple the input signal to an inverter that is self-biased at the threshold voltage for the inverter. The AC coupling of the input signal permits the input signal to “ride on” the threshold voltage and transition the inverter between states depending on the value of the input signal. The inverter can be biased at the threshold voltage by connecting the output of the inverter in feedback with the input of the inverter using one or more resistors.

Claims

1. A system for adjusting a voltage level of a clock signal, the system comprising:

an input connection to receive an input clock signal having a first voltage level;

an output connection to provide an output signal having a second voltage level greater than the first level;

a capacitor coupled to the input connection;

a first inverter coupled to the capacitor at an input node, the first inverter configured to provide the output signal to the output connection, the output connection connected in a feedback loop with the input node, the feedback loop configured to bias the first inverter at a threshold voltage for the first inverter, the first inverter comprising;

a first transistor coupled to the input node, the output connection, and a voltage source, the voltage source providing a voltage at the second voltage level, wherein the threshold voltage is based on the second voltage level;

a second transistor coupled to the input node, the output connection, and ground; and

a resistor coupled between the input node and the output connection to form the feedback loop, wherein the capacitor is coupled to the input node to AC couple the input clock signal onto the threshold voltage such that changes in the input clock signal result in changes in the output signal from the first inverter; and

a switch coupled between the capacitor and the first inverter, the switch having a first state to connect the capacitor and the first inverter and a second state to disconnect the capacitor and the first inverter.

2. The system of claim 1, wherein the first transistor comprises an n-channel metal oxide semiconductor field effect transistor (MOSFET) and the second transistor comprises a p-channel MOSFET.

3. The system of claim 1, wherein the capacitor is a high pass filter configured to remove frequencies below a threshold frequency.

4. The system of claim 1, wherein the output signal has a duty cycle substantially equal to a duty cycle of the input clock signal.

5. The system of claim 1, wherein the resistor comprises a first resistor connected in series with a second resistor.

6. The system of claim 1, further comprising a second inverter coupled to the output connection of the first inverter to invert the output signal.

7. A level shifting circuit for a signal, the level shifting circuit comprising:

an input connection to receive an input signal having a first voltage level and a low voltage level;

an output connection to provide an output signal having a second voltage level greater than the first voltage level;

a capacitor coupled to the input connection to receive the input signal;

an output module coupled to the capacitor to receive the input signal and to the output connection to provide the output signal, the output module comprising a switching circuit, the switching circuit having an input node and an output node connected in a feedback loop, wherein the feedback loop of the switching circuit biases the switching circuit at a threshold voltage,

wherein the switching circuit switches to a first state in response to an input voltage at the input node being greater than the threshold voltage and switches to a second state in response to the input voltage at the input node being less than the threshold voltage,

wherein the output signal is based on the switching circuit switching between the first state and the second state, and

wherein the capacitor is configured to AC couple the input signal onto the threshold voltage such that a portion of the input signal at the first voltage level results in the input voltage at the input node being greater than the threshold voltage and a portion of the input signal at the low voltage level results in the input voltage at the input node being less than the threshold voltage; and

a switch coupled between the capacitor and the output module, the switch having a first state to connect the capacitor and the output module and a second state to disconnect the capacitor and the output module.

8. The level shifting circuit of claim 7, wherein the switching circuit is configured to output a signal at the second voltage level in response to the switching circuit switching to the second state and configured to output a signal at a third voltage level less than the first voltage level in response to the switching circuit switching to the first state.

9. The level shifting circuit of claim 8, wherein the third voltage level comprises a ground voltage level.

10. The level shifting circuit of claim 7, wherein the switching circuit comprises a first inverter, further comprising a second inverter coupled to the output connection, the second inverter configured to receive the output signal and to provide an inverted version of the output signal.

11. The level shifting circuit of claim 10, wherein the second inverter output signal has a polarity that is substantially equal to the input signal.

12. The level shifting circuit of claim 7, wherein the feedback loop comprises a resistor coupled between the input node and the output node.

13. The level shifting circuit of claim 12, wherein the resistor comprises a first resistor connected in series with a second resistor.

14. The level shifting circuit of claim 13, wherein the switch is a first switch and the feedback loop further comprises a second switch coupled between the first resistor and the second resistor, wherein the second switch has a first state to connect the input node and the output node and a second state to disconnect the input node and the output node.

15. The level shifting circuit of claim 7, wherein the capacitor is configured to remove frequencies below a threshold frequency.

16. The level shifting circuit of claim 7, wherein the output signal has a duty cycle substantially equal to a duty cycle of the input signal.

17. The level shifting circuit of claim 7, wherein the switching circuit comprises:

a first transistor coupled to the input node, the output node and a voltage source, the voltage source providing a voltage at the second voltage level; and

a second transistor coupled to the input node, the output node and ground.

18. The level shifting circuit of claim 17, wherein the first transistor comprises an n-channel metal oxide semiconductor field effect transistor (MOSFET) and the second transistor comprises a p-channel MOSFET.

19. The level shifting circuit of claim 7, further comprising a buffer element coupled between the input connection and the capacitor, wherein the buffer element is configured to buffer the input signal.

20. A method for shifting the voltage level of a signal, the method comprising:

biasing a switching circuit at a threshold voltage for the switching circuit;

AC coupling an input signal at a first voltage level onto the threshold voltage with a capacitor to generate an input voltage for the switching circuit;

switching the switching circuit to a first state in response to the input voltage being greater than the threshold voltage, wherein the input voltage is greater than the threshold voltage during a first portion of the input signal having a first signal voltage;

switching the switching circuit to a second state in response to the input voltage being less than the threshold voltage, wherein the input voltage is less than the threshold voltage during a second portion of the input signal having a second signal voltage that is less than the first signal voltage;

generating a switching circuit output signal at a second voltage level greater than the first voltage level based on switching the switching circuit to the first state and switching the switching circuit to the second state;

providing an output signal at the second voltage level based on the switching circuit output signal; and

decoupling the capacitor from the switching circuit in response to the switching circuit being deactivated.

21. The method of claim 20, wherein the biasing the switching circuit includes coupling an output node of the switching circuit to an input node of the switching circuit in a feedback loop, and wherein the feedback loop has at least one resistor.

22. The method of claim 20, wherein the providing an output signal includes inverting the switching circuit output signal with an inverter.

23. The method of claim 20, wherein the generating a switching circuit output signal includes setting the switching circuit output signal at a first value in response to switching the switching circuit to the first state and setting the switching circuit output signal to a second value in response to switching the switching circuit to the second state.

24. The method of claim 23, wherein:

the switching circuit comprises a first transistor coupled to a second transistor, the first transistor coupled to a voltage source providing a voltage at the second voltage level, the second transistor coupled to ground;

setting the switching circuit output signal at a first value includes coupling an output node of the switching circuit to ground with the second transistor; and

setting the switching circuit output signal to a second value includes coupling the output node of the switching circuit to the voltage source with the first transistor.

25. The method of claim 20, further comprising removing frequencies below a threshold frequency with the capacitor.